H8SSLASH2214 datasheet(61/936 Pages) RENESAS

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Section 1 Overview

Rev.4.00 Sep. 18, 2008 Page 1 of 872

REJ09B0189-0400

Section 1 Overview

1.1

Overview

The H8S/2214 Group is a microcomputer (MCU: microcomputer unit), built around the H8S/2000

CPU, employing Renesas' proprietary architecture, and equipped with the on-chip peripheral

functions necessary for system configuration.

The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general

registers and a concise, optimized instruction set designed for high-speed operation, and can

address a 16-Mbyte linear address space. The instruction set is upward-compatible with H8/300

and H8/300H CPU instructions at the object-code level, facilitating migration from the H8/300,

H8/300L, or H8/300H Series.

On-chip peripheral functions required for system configuration include DMA controller (DMAC)

data transfer controller (DTC) bus masters, ROM and RAM memory, a 16-bit timer-pulse unit

(TPU), watchdog timer (WDT), serial communication interface (SCI), D/A converter, and I/O

ports.

The on-chip ROM is either flash memory (F-ZTAT™*) or masked ROM, with a capacity of 128

kbytes. ROM is connected to the CPU via a 16-bit data bus, enabling both byte and word data to

be accessed in one state. Instruction fetching has been speeded up, and processing speed increased.

Four operating modes, modes 4 to 7, are provided, and there is a choice of single-chip mode or

external expansion mode.

The features of the H8S/2214 Group are shown in table 1.1.

Note: * F-ZTAT is a trademark of Renesas Technology, Corp.

H8S/2214 数据表(PDF) 61 Page - Renesas Technology Corp