H8SSLASH2214 datasheet(23/936 Pages) RENESAS

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Rev.4.00 Sep. 18, 2008 Page xxiii of lx

REJ09B0189-0400

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Page

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12.4 SCI Interrupts 518

Note added

... The TDRE flag is cleared to 0 automatically when data transfer

is performed by the DMAC or DTC*. ...

... The RDRF flag is cleared to 0 automatically when data transfer

is performed by the DMAC or DTC*. ...

Note : * The flag is cleared when DISEL is 0 and furthermore the

transfer counter is not 0.

12.5 Usage Notes

(1) Module Stop

Mode Settings

520

Description added

(8) Restrictions on

Use of DMAC or

DTC

523

Description added

(b) When RDR is read by the DMAC or DTC, be sure to set the

activation source to the relevant SCI reception end interrupt

(RXI).

only when the DTC DISEL bit is 0 and furthermore the transfer

counter is not 0. Therefore the CPU must clear the flags when

either DISEL is 1 or when DISEL is 0 and furthermore the

transfer counter is 0. In particular, note that during

transmission, data will not be transmitted correctly unless the

CPU clears the TDRE flag.

17.6.3 Setting

Oscillation

Stabilization Time

after Clearing

Software Standby

Mode

Table 17.4

Oscillation

Stabilization Time

Settings

630

Table amended

STS2 STS1 STS0 Standby Time 16 MHz 13 MHz 10 MHz 8 MHz

6 MHz

4 MHz

2 MHz

Unit

8192 states

0.51

0.63

0.82

1.0

1.4

2.0

4.1

16384 states

1.0

1.3

1.6

2.0

2.7

4.1

8.2

32768 states

2.0

2.5

3.3

4.1

5.5

8.2

16.4

65536 states

4.1

5.0

6.6

8.2

10.9

16.4

32.8

131072 states

8.2

10.1

13.1

16.4

21.8

32.8

65.5

262144 states

16.4

20.2

26.2

32.8

43.7

65.5

131.1

2048 states

0.13

0.16

0.20

0.26

0.34

0.51

1.0

16 states

1.0

1.2

1.6

2.0

2.7

4.0

8.0

µs

: Recommended time setting

18.7 Usage Note

• Characteristics of

the F-ZTAT and

Mask ROM Versions

659

Title added

• General Notes on

Printed Circuit

Board Deign

Description added

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