H8SSLASH2214 datasheet(40/936 Pages) RENESAS

40 / 936 page

Rev.4.00 Sep. 18, 2008 Page xl of lx

REJ09B0189-0400

12.1.3 Pin Configuration.................................................................................................. 457

12.1.4 Register Configuration.......................................................................................... 458

12.2

Register Descriptions ......................................................................................................... 459

12.2.1 Receive Shift Register (RSR) ............................................................................... 459

12.2.2 Receive Data Register (RDR) ............................................................................... 459

12.2.3 Transmit Shift Register (TSR) .............................................................................. 460

12.2.4 Transmit Data Register (TDR).............................................................................. 460

12.2.5 Serial Mode Register (SMR) ................................................................................ 461

12.2.6 Serial Control Register (SCR)............................................................................... 464

12.2.7 Serial Status Register (SSR) ................................................................................. 467

12.2.8 Bit Rate Register (BRR) ....................................................................................... 472

12.2.9 Smart Card Mode Register (SCMR) ..................................................................... 480

12.2.10 Serial Extended Mode Register 0 (SEMR0) ......................................................... 481

12.2.11 Module Stop Control Register B (MSTPCRB)..................................................... 486

12.3

Operation ........................................................................................................................... 487

12.3.1 Overview............................................................................................................... 487

12.3.2 Operation in Asynchronous Mode ........................................................................ 490

12.3.3 Multiprocessor Communication Function............................................................. 501

12.3.4 Operation in Clocked Synchronous Mode ............................................................ 509

12.4

SCI Interrupts..................................................................................................................... 518

12.5

Usage Notes ....................................................................................................................... 520

Section 13 D/A Converter .................................................................................531

13.1

Overview............................................................................................................................ 531

13.1.1 Features................................................................................................................. 531

13.1.2 Block Diagram...................................................................................................... 532

13.1.3 Pin Configuration.................................................................................................. 533

13.1.4 Register Configuration.......................................................................................... 533

13.2

Register Descriptions ......................................................................................................... 534

13.2.1 D/A Data Register 0 (DADR0)............................................................................. 534

13.2.2 D/A Control Register (DACR) ............................................................................. 534

13.2.3 Module Stop Control Register C (MSTPCRC)..................................................... 535

13.3

Operation ........................................................................................................................... 536

Section 14 RAM ................................................................................................539

14.1

Overview............................................................................................................................ 539

14.1.1 Block Diagram...................................................................................................... 539

14.1.2 Register Configuration.......................................................................................... 540

14.2

Register Descriptions ......................................................................................................... 540

14.2.1 System Control Register (SYSCR) ....................................................................... 540

14.3

Operation ........................................................................................................................... 541

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