H8SSLASH2214 datasheet(42/936 Pages) RENESAS

42 / 936 page

Rev.4.00 Sep. 18, 2008 Page xlii of lx

REJ09B0189-0400

15.13.1 Socket Adapter Pin Correspondence Diagram...................................................... 583

15.13.2 Programmer Mode Operation ............................................................................... 585

15.13.3 Memory Read Mode ............................................................................................. 586

15.13.4 Auto-Program Mode ............................................................................................. 590

15.13.5 Auto-Erase Mode.................................................................................................. 592

15.13.6 Status Read Mode ................................................................................................. 594

15.13.7 Status Polling ........................................................................................................ 595

15.13.8 Programmer Mode Transition Time ..................................................................... 596

15.13.9 Notes on Memory Programming........................................................................... 597

15.14 Flash Memory and Power-Down States............................................................................. 597

15.14.1 Note on Power-Down States ................................................................................. 598

15.15 Flash Memory Programming and Erasing Precautions ...................................................... 598

15.16 Note on Switching from F-ZTAT Version to Masked ROM Version ............................... 604

Section 16 Clock Pulse Generator .....................................................................605

16.1

Overview............................................................................................................................ 605

16.1.1 Block Diagram...................................................................................................... 605

16.1.2 Register Configuration.......................................................................................... 606

16.2

Register Descriptions ......................................................................................................... 606

16.2.1 System Clock Control Register (SCKCR) ............................................................ 606

16.2.2 Low-Power Control Register (LPWRCR) ............................................................ 607

16.3

System Clock Oscillator..................................................................................................... 609

16.3.1 Connecting a Crystal Resonator............................................................................ 609

16.3.2 External Clock Input ............................................................................................. 611

16.4

Duty Adjustment Circuit.................................................................................................... 615

16.5

Medium-Speed Clock Divider ........................................................................................... 615

16.6

Bus Master Clock Selection Circuit ................................................................................... 615

16.7

Note on Crystal Resonator ................................................................................................. 615

Section 17 Power-Down Modes ........................................................................617

17.1

Overview............................................................................................................................ 617

17.1.1 Register Configuration.......................................................................................... 620

17.2

Register Descriptions ......................................................................................................... 620

17.2.1 Standby Control Register (SBYCR) ..................................................................... 620

17.2.2 System Clock Control Register (SCKCR) ............................................................ 622

17.2.3 Module Stop Control Register (MSTPCR) ........................................................... 623

17.3

Medium-Speed Mode......................................................................................................... 624

17.4

Sleep Mode ........................................................................................................................ 625

17.4.1 Sleep Mode ........................................................................................................... 625

17.4.2 Clearing Sleep Mode............................................................................................. 625

17.5

Module Stop Mode ............................................................................................................ 626

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