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H8S/2214 数据表(PDF) 11 Page - Renesas Technology Corp |
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H8S/2214 数据表(HTML) 11 Page - Renesas Technology Corp |
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11 / 936 page ![]() Rev.4.00 Sep. 18, 2008 Page xi of lx REJ09B0189-0400 Item Page Revisions (See Manual for Details) 7.5.9 DMAC Bus Cycles (Dual Address Mode) (2) Full Address Mode (Cycle Steal Mode) 234 Description amended Either a one-byte or a one-word transfer is performed for each transfer request, and after the transfer the bus is released. 8.2.5 DTC Transfer Count Register A (CRA) 258 Description amended In repeat mode or block transfer mode, CRA is divided into two parts: the upper 8 bits (CRAH) and the lower 8 bits (CRAL). In repeat mode, CRAH holds the transfer count and CRAL functions as an 8-bit transfer counter (1 to 256). In block transfer mode, CRAH holds the block size and functions as an 8-bit block size counter (1 to 256). CRAL is decremented by 1 every time data is transferred and when the counter value becomes H'00 the contents of CRAH are transferred. This operation is repeated. 8.3.1 Overview Figure 8.2 Flowchart of DTC Operation 262 Note added Note: * See the section on the corresponding peripheral module for details on the content of the processing required for interrupt handling. Clear an activation flag End No Yes Transfer Counter = 0 or DISEL = 1 Clear DTCER Interrupt exception handling * 8.3.2 Activation Sources 264 Description added ... The activation source flag, in the case of RXI0, for example, is the RDRF flag of SCI0. Since there are multiple factors that can initiate DTC operation, the flag that initiated the transfer is not cleared after the last byte (or word) is transferred. The corresponding interrupt handler must perform the required processing. |
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