H8SSLASH2214 datasheet(340/936 Pages) RENESAS

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Section 8 Data Transfer Controller (DTC)

Rev.4.00 Sep. 18, 2008 Page 280 of 872

REJ09B0189-0400

8.4

Interrupts

An interrupt request is issued to the CPU when the DTC finishes the specified number of data

transfers, or a data transfer for which the DISEL bit was set to 1. In the case of interrupt activation,

the interrupt set as the activation source is generated. These interrupts to the CPU are subject to

CPU mask level and interrupt controller priority level control.

In the case of activation by software, a software activated data transfer end interrupt (SWDTEND)

is generated.

When the DISEL bit is 1 and one data transfer has ended, or the specified number of transfers

have ended, after data transfer ends, the SWDTE bit is held at 1 and an SWDTEND interrupt is

generated. The interrupt handling routine should clear the SWDTE bit to 0.

When the DTC is activated by software, an SWDTEND interrupt is not generated during a data

transfer wait or during data transfer even if the SWDTE bit is set to 1.

8.5

Usage Notes

(1) Module Stop

When the MSTPA6 bit in MSTPCRA is set to 1, the DTC clock stops, and the DTC enters the

module stop state. However, 1 cannot be written in the MSTPA6 bit while the DTC is operating.

See section 17, Power-Down Modes, for details.

(2) On-Chip RAM

The MRA, MRB, SAR, DAR, CRA, and CRB registers are all located in on-chip RAM. When the

DTC is used, the RAME bit in SYSCR must not be cleared to 0.

(3) DMAC Transfer End Interrupt

When DTC transfer is activated by a DMAC transfer end interrupt, the DMAC's DTE bit is not

subject to DTC control, regardless of the transfer counter and DISEL bit, and the write data has

priority. Consequently, an interrupt request is not sent to the CPU when the DTC transfer counter

reaches 0.

(4) DTCE Bit Setting

For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR. If all interrupts

are masked, multiple activation sources can be set at one time by writing data after executing a

dummy read on the relevant register.

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