H8SSLASH2214 datasheet(384/936 Pages) RENESAS

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Section 9 I/O Ports

Rev.4.00 Sep. 18, 2008 Page 324 of 872

REJ09B0189-0400

(2) Port B Data Register (PBDR)

PB7DR

R/W

PB6DR

R/W

PB5DR

R/W

PB4DR

R/W

PB3DR

R/W

PB0DR

R/W

PB2DR

R/W

PB1DR

R/W

Bit

Initial value :

R/W

PBDR is an 8-bit readable/writable register that stores output data for the port B pins (PB7 to

PB0).

PBDR is initialized to H'00 by a power-on reset and in hardware standby mode. It retains its

previous state after a manual reset and in software standby mode.

(3) Port B Register (PORTB)

PB7

—*

PB6

—*

PB5

—*

PB4

—*

PB3

—*

PB0

—*

PB2

—*

PB1

—*

Bit

Initial value :

R/W

Note: * Determined by the state of pins PB7 to PB0.

PORTB is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of

output data for the port B pins (PB7 to PB0) must always be performed on PBDR.

If a port B read is performed while PBDDR bits are set to 1, the PBDR values are read. If a port B

read is performed while PBDDR bits are cleared to 0, the pin states are read.

After a power-on reset and in hardware standby mode, PORTB contents are determined by the pin

states, as PBDDR and PBDR are initialized. PORTB retains its previous state after a manual reset

and in software standby mode.

(4) Port B MOS Pull-Up Control Register (PBPCR)

PB7PCR

R/W

PB6PCR

R/W

PB5PCR

R/W

PB4PCR

R/W

PB3PCR

R/W

PB0PCR

R/W

PB2PCR

R/W

PB1PCR

R/W

Bit

Initial value :

R/W

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