H8SSLASH2214 datasheet(398/936 Pages) RENESAS

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Section 9 I/O Ports

Rev.4.00 Sep. 18, 2008 Page 338 of 872

REJ09B0189-0400

9.10.2

Table 9.18 shows the port D register configuration.

Table 9.18

Port D Registers

Name

Abbreviation

R/W

Initial Value

Address*

Port D data direction register

PDDDR

H'00

H'FE3C

Port D data register

PDDR

R/W

H'00

H'FF0C

Port D register

PORTD

Undefined

H'FFBC

Port D MOS pull-up control register

PDPCR

R/W

H'00

H'FE43

Note: * Lower 16 bits of the address.

(1) Port D Data Direction Register (PDDDR)

PD7DDR

PD6DDR

PD5DDR

PD4DDR

PD3DDR

PD0DDR

PD2DDR

PD1DDR

Bit

Initial value :

R/W

PDDDR is an 8-bit write-only register, the individual bits of which specify input or output for the

pins of port D. PDDDR cannot be read; if it is, an undefined value will be read.

Setting a PDDDR bit to 1 makes the corresponding port C pin an output pin, while clearing the bit

to 0, makes the pin an input pin. Since this register is a write-only register, do not use bit

manipulation instructions to write to this register. See section 2.10.4, Access Methods for

Registers with Write-Only Bits.

PDDDR is initialized to H'00 by a power-on reset and in hardware standby mode. It retains its

previous state after a manual reset and in software standby mode.

(a) Modes 4 to 6

The input/output direction settings in PDDDR are ignored, and port D pins automatically

function as data input/output pins.

(b) Mode 7

Setting a PDDDR bit to 1 makes the corresponding port D pin an output port, while clearing

the bit to 0 makes the pin an input port.

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