H8SSLASH2214 datasheet(439/936 Pages) RENESAS

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Section 10 16-Bit Timer Pulse Unit (TPU)

Rev.4.00 Sep. 18, 2008 Page 379 of 872

REJ09B0189-0400

10.2.4

Timer Interrupt Enable Register (TIER)

—

R/W

—

TCIEV

R/W

TGIED

R/W

TGIEA

R/W

TGIEC

R/W

TGIEB

R/W

Bit

Initial value

R/W

Channel 0: TIER0

—

R/W

—

TCIEU

R/W

TCIEV

R/W

—

TGIEA

R/W

—

TGIEB

R/W

Channel 1: TIER1

Channel 2: TIER2

Bit

Initial value

R/W

The TIER registers are 8-bit registers that control enabling or disabling of interrupt requests for

each channel. The TPU has three TIER registers, one for each channel. The TIER registers are

initialized to H'40 by a reset, and in hardware standby mode.

Bit 7—Reserved: Only 0 should be written to this bit.

Bit 6—Reserved: Read-only bit, always read as 1.

Bit 5—Underflow Interrupt Enable (TCIEU): Enables or disables interrupt requests (TCIU) by

the TCFU flag when the TCFU flag in TSR is set to 1 in channels 1 and 2.

In channel 0, bit 5 is reserved. It is always read as 0 and cannot be modified.

Bit 5

TCIEU

Description

Interrupt requests (TCIU) by TCFU disabled

(Initial value)

Interrupt requests (TCIU) by TCFU enabled

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