H8SSLASH2214 datasheet(477/936 Pages) RENESAS

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Section 10 16-Bit Timer Pulse Unit (TPU)

Rev.4.00 Sep. 18, 2008 Page 417 of 872

REJ09B0189-0400

(1) Input Capture/Compare Match Interrupt

An interrupt is requested if the TGIE bit in TIER is set to 1 when the TGF flag in TSR is set to 1

by the occurrence of a TGR input capture/compare match on a particular channel. The interrupt

request is cleared by clearing the TGF flag to 0. The TPU has eight input capture/compare match

interrupts, four for channel 0, and two each for channels 1 and 2.

(2) Overflow Interrupt

An interrupt is requested if the TCIEV bit in TIER is set to 1 when the TCFV flag in TSR is set to

1 by the occurrence of TCNT overflow on a channel. The interrupt request is cleared by clearing

the TCFV flag to 0. The TPU has three overflow interrupts, one for each channel.

(3) Underflow Interrupt

An interrupt is requested if the TCIEU bit in TIER is set to 1 when the TCFU flag in TSR is set to

1 by the occurrence of TCNT underflow on a channel. The interrupt request is cleared by clearing

the TCFU flag to 0. The TPU has two overflow interrupts, one each for channels 1 and 2.

10.5.2

DTC and DMAC Activation

(1) DTC Activation

The DTC can be activated by the TGR input capture/compare match interrupt for a channel. For

details, see section 8, Data Transfer Controller (DTC).

A total of eight TPU input capture/compare match interrupts can be used as DTC activation

sources, four each for channel 0, and two each for channels 1 and 2.

(2) DMAC Activation

The DMAC can be activated by the TGRA input capture/compare match interrupt for a channel.

For details, see section 7, DMA Controller (DMAC).

With the TPU, a total of three TGRA input capture/compare match interrupts can be used as

DMAC activation sources, one for each channel.

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