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H8S/2214 数据表(PDF) 509 Page - Renesas Technology Corp |
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H8S/2214 数据表(HTML) 509 Page - Renesas Technology Corp |
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509 / 936 page  Section 11 Watchdog Timer (WDT) Rev.4.00 Sep. 18, 2008 Page 449 of 872 REJ09B0189-0400 11.3.4 Timing of Setting of Watchdog Timer Overflow Flag (WOVF) With WDT, the WOVF bit in RSTCSR is set to 1 if TCNT overflows in watchdog timer mode. If TCNT overflows while the RSTE bit in RSTCSR is set to 1, an internal reset signal is generated for the entire chip. This timing is illustrated in figure 11.7. φ TCNT H'FF H'00 Overflow signal (internal signal) Internal reset signal WOVF 518 states (WDT) Figure 11.7 Timing of WOVF Setting 11.4 Interrupts During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI). The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR. OVF must be cleared to 0 in the interrupt handling routine. |
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