H8SSLASH2214 datasheet(108/936 Pages) RENESAS

108 / 936 page

Section 2 CPU

Rev.4.00 Sep. 18, 2008 Page 48 of 872

REJ09B0189-0400

(3) Effective Address Extension

Eight, 16, or 32 bits specifying immediate data, an absolute address, or a displacement.

(4) Condition Field

Specifies the branching condition of Bcc instructions.

2.6.5

Notes on Use of Bit-Manipulation Instructions

The BSET, BCLR, BNOT, BST, and BIST instructions read a byte of data, carry out bit

manipulation, then write back the byte of data. Caution is therefore required when using these

instructions on a register containing write-only bits, or a port.

The BCLR instruction can be used to clear internal I/O register flags to 0. In this case, the relevant

flag need not be read beforehand if it is clear that it has been set to 1 in an interrupt handling

routine, etc.

See section 2.10.3, Bit Manipulation Instructions Usage Notes, for details.

2.7

Addressing Modes and Effective Address Calculation

2.7.1

Addressing Mode

The CPU supports the eight addressing modes listed in table 2.4. Each instruction uses a subset of

these addressing modes. Arithmetic and logic instructions can use the register direct and

immediate modes. Data transfer instructions can use all addressing modes except program-counter

relative and memory indirect. Bit manipulation instructions use register direct, register indirect, or

absolute addressing mode to specify an operand, and register direct (BSET, BCLR, BNOT, and

BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand.

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