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H8S/2214 数据表(PDF) 198 Page - Renesas Technology Corp |
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H8S/2214 数据表(HTML) 198 Page - Renesas Technology Corp |
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198 / 936 page  Section 6 Bus Controller Rev.4.00 Sep. 18, 2008 Page 138 of 872 REJ09B0189-0400 6.3.5 Chip Select Signals The H8S/2214 Group can output chip select signals ( CS0 to CS7) to areas 0 to 7, the signal being driven low when the corresponding external space area is accessed. Figure 6.3 shows an example of CSn (n = 0 to 7) output timing. Enabling or disabling of the CSn signal is performed by setting the data direction register (DDR) for the port corresponding to the particular CSn pin. In ROM-disabled expansion mode, the CS0 pin is placed in the output state after a power-on reset. Pins CS1 to CS7 are placed in the input state after a power-on reset, and so the corresponding DDR should be set to 1 when outputting signals CS1 to CS7. In ROM-enabled expansion mode, pins CS0 to CS7 are all placed in the input state after a power- on reset, and so the corresponding DDR should be set to 1 when outputting signals CS0 to CS7. For details, see section 9, I/O Ports. Bus cycle T1 T2 T3 Area n external address Address bus φ CSn Figure 6.3 CSn Signal Output Timing (n = 0 to 7) |
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