H8SSLASH2214 datasheet(299/936 Pages) RENESAS

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Section 7 DMA Controller

Rev.4.00 Sep. 18, 2008 Page 239 of 872

REJ09B0189-0400

(6)

DREQ Level Activation Timing (Normal Mode)

Set the DTA bit for the channel for which the

DREQ pin is selected to 1.

Figure 7.22 shows an example of

DREQ level activated normal mode transfer.

[1]

[2] [5]

[3] [6]

[4] [7]

Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible.

Acceptance after transfer enabling; the

DREQ pin low level is sampled on the rising

edge of

φ, and the request is held.

The request is cleared at the next bus break, and activation is started in the DMAC.

The DMA cycle is started.

Acceptance is resumed after the write cycle is completed.

(As in [1], the

DREQ pin low level is sampled on the rising edge of φ, and the request is held.)

DMA

read

DMA

write

Address bus

DREQ

Idle

Write

Idle

Bus

release

DMA control

Channel

Write

Idle

Transfer

source

Bus

release

DMA

read

DMA

write

Bus

release

Request

Minimum of 2 cycles

[1]

[3]

[2]

Minimum of 2 cycles

[4]

[6]

[5]

[7]

Acceptance resumes

Transfer

destination

Transfer

source

Transfer

destination

Request

Read

Request clear period

Read

Request clear period

Figure 7.22 Example of

DREQ Level Activated Normal Mode Transfer

DREQ pin sampling is performed every cycle, with the rising edge of the next φ cycle after the

end of the DMABCR write cycle for setting the transfer enabled state as the starting point.

When the

DREQ pin low level is sampled while acceptance by means of the DREQ pin is

possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the

request is cleared. After the end of the write cycle, acceptance resumes,

DREQ pin low level

sampling is performed again, and this operation is repeated until the transfer ends.

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