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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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GXM 数据表(PDF) 101 Page - National Semiconductor (TI) |
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GXM 数据表(HTML) 101 Page - National Semiconductor (TI) |
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101 / 244 page  Revision 3.1 101 www.national.com Integrated Functions (Continued) 4.2.5 Internal Bus Interface Unit Registers The Internal Bus Interface Unit maps 100h locations start- ing at GX_BASE+8000h. Refer to Section 4.1.2 “Control Registers” on page 94 for instructions on accessing these registers. Table 4-9 summarizes the four 32-bit registers contained in the Internal Bus Interface Unit and Table 4-10 gives the register/bit formats. Table 4-9. Internal Bus Interface Unit Register Summary GX_BASE+ Memory Offset Type Name/Function Default Value 8000h-8003h R/W BC_DRAM_TOP Top of DRAM: Contains the highest available address of system memory not including the memory that is set aside for graphics memory, which corresponds to 1 GByte of memory. The largest possible value for the register is 3FFFFFFFh. 3FFFFFFFh 8004h-8007h R/W BC_XMAP_1 Memory X-Bus Map Register 1 (A and B Region Control: Contains the region control of the A and B regions and the SMI controls required for VGA emulation. PCI access to internal registers and the A20M function are also controlled by this register. 00000000h 8008h-800Bh R/W BC_XMAP_2 Memory X-Bus Map Register 2 (C and D Region Control): Contains region con- trol fields for eight regions in the address range C0h through DCh. 00000000h 800Ch-800Fh R/W BC_XMAP_3 Memory X-Bus Map Register 3 (E and F Region Control): Contains the region control fields for memory regions in the address range E0h through FCh. 00000000h Table 4-10. Internal Bus Interface Unit Registers Bit Name Description GX_BASE+8000h-8003h BC_DRAM_TOP Register (R/W) Default Value = 3FFFFFFFh 31:30 RSVD Reserved: Set to 0. 29:17 TOP OF DRAM Top of DRAM: Maximum value is FFFh. 16:0 1FFFF Granularity: Must be set to 1FFFFh (128 KB). GX_BASE+8004h-8007h BC_XMAP_1 Register (R/W) Default Value = 00000000h 31:29 RSVD Reserved: Set to 0. 28 GEB8 Graphics Enable for B8 Region: Allow memory R/W operations for address range B8000h-BFFFFh be directed to the graphics pipeline: 0 = Disable; 1 = Enable. (Used for VGA emulation.) 27:24 B8 B8 Region: Region control field for address range B8000h-BFFFFh. Note: Refer to Table 4-11 for decode. 23 RSVD Reserved: Set to 0. 22 PRAE PCI Register Access Enable: Allow PCI Slave to access internal registers on the X-Bus: 0 = Disable; 1 = Enable. 21 A20M Address Bit 20 Mask: Address bit 20 is always forced to a zero except for SMI accesses: 0 = Disable; 1 = Enable. 20 GEB0 Graphics Enable for B0 Region: Allow memory R/W operations for address range B0000h-B7FFFh be directed to the graphics pipeline: 0 = Disable; 1 = Enable. (Used for VGA emulation.) 19:16 B0 B0 Region: Region control field for address range B0000h-B7FFFh. Note: Refer to Table 4-11 for decode. 15 SMID SMID: All I/O accesses for address range 3D0h-3DFh generate an SMI: 0 = Disable; 1 = Enable. (Used for VGA virtualization.) 14 SMIC SMIC: All I/O accesses for address range 3C0h-3CFh generate an SMI: 0 = Disable; 1 = Enable. (Used for VGA virtualization.) 13 SMIB SMIB: All I/O accesses for address range 3B0h-3BFh generate an SMI: 0 = Disable; 1 = Enable (Used for VGA virtualization.) |
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