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GXM 数据表(PDF) 105 Page - National Semiconductor (TI) |
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GXM 数据表(HTML) 105 Page - National Semiconductor (TI) |
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105 / 244 page  Revision 3.1 105 www.national.com Integrated Functions (Continued) 4.3.2 Memory Organizations The memory controller supports JEDEC standard synchronous DRAMs in 16 Mb and 64 Mb configurations. Supported configurations are shown in Table 4-12. Table 4-12. Synchronous DRAM Configurations Depth Organization Row Address Column Address Bank Address Total # of Address bits 1 1 Mx16 A10-A0 A7-A0 BA0 20 2 2 Mx8 A10-A0 A8-A0 BA0 21 2 Mx32 A10-A0 A7-A0 BA1-BA0 21 2 Mx32 A10-A0 A8-A0 BA0 21 2 Mx32 A11-A0 A6-A0 BA1-BA0 21 2 Mx32 A12-A0 A6-A0 BA0 21 4 4 Mx4 A10-A0 A9-A0 BA0 22 4 Mx16 A11-A0 A7-A0 BA1-BA0 22 4 Mx16 A12-A0 A7-A0 BA0 22 4 Mx16 A10-A0 A9-A0 BA0 22 8 8 Mx8 A11-A0 A8-A0 BA1-BA0 23 8 Mx8 A12-A0 A8-A0 BA0 23 8 Mx32 A11-A0 A8-A0 BA1-BA0 23 8 Mx32 A12-A0 A7-A0 BA1-BA0 23 16 16 Mx4 A11-A0 A9-A0 BA1-BA0 24 16 Mx4 A12-A0 A9-A0 BA0 24 16 Mx16 A12-A0 A8-A0 BA1-BA0 24 16 Mx16 A11-A0 A9-A0 BA1-BA0 24 32 32 Mx8 A12-A0 A9-A0 BA1-BA0 25 64 64 Mx4 A12-A0 A9-A0,A11 BA1-BA0 26 |
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