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108

Revision 3.1

Integrated Functions (Continued)

4.3.4

Memory Controller Register Description

The Memory Controller maps 100h locations starting at

GX_BASE+8400h. Refer to Section 4.1.2 “Control Regis-

ters” on page 94 for instructions on accessing these regis-

ters.

Table 4-15 summarizes the 32-bit registers contained in

the memory controller. Table 4-16 gives detailed regis-

ter/bit formats.

Table 4-15. Memory Controller Register Summary

GX_BASE+

Memory Offset

Type

Name/Function

Default Value

8400h-8403h

R/W

MC_MEM_CNTRL1

Memory Controller Control Register 1: Memory controller configuration informa-

tion e.g., refresh interval, SDCLK ratio, etc.

248C0040h

8404h-8407h

R/W

MC_MEM_CNTRL2

Memory Controller Control Register 2: Memory controller configuration informa-

tion to control SDCLK.

00000801h

8408h-840Bh

R/W

MC_BANK_CFG

Memory Controller Bank Configuration: Contains the configuration information for

the each of the two DIMMs in the memory array. BIOS programs this register dur-

ing boot by running an autosizing routine on the memory.

41104110h

840Ch-840Fh

R/W

MC_SYNC_TIM1

Memory Controller Synchronous Timing Register 1: SDRAM memory timing

information - This register controls the memory timing of all four banks of DRAM.

BIOS programs this register based on the processor frequency and the SDCLK

divide ratio.

2A733225h

8414h-8417h

R/W

MC_GBASE_ADD

Memory Controller Graphics Base Address Register: This register sets the

graphics memory base address, which is programmable on 512 KB boundaries.

The display controller and the graphics pipeline generate a 20-bit DWORD offset

that is added to the graphics memory base address to form the physical memory

address. Typically, the graphics memory region is located at the top of physical

memory.

00000000h

8418h-841Bh

R/W

MC_DR_ADD

Memory Controller Dirty RAM Address Register: This register is used to set the

Dirty RAM address index for processor diagnostic access. This register should be

initialized before accessing the MC_DR_ACC register

00000000h

841Ch-841Fh

R/W

MC_DR_ACC

Memory Controller Dirty RAM Access Register: This register is used to access

the Dirty RAM. A read/write to this register will access the Dirty RAM at the

address specified in the MC_DR_ADD register.

0000000xh

Table 4-16. Memory Controller Registers

Bit

Name

Description

GX_BASE+ 8400h-8403h

MC_MEM_CNTRL1 (R/W)

Default Value = 248C0040h

31:29

MDHDCTL

MD High Drive Control: Controls the high drive and slew rate of the memory data bus (MD[63:0]):

000 = Tristate

001 = Smallest drive strength

010 -110 = Represents gradual drive strength increase

111 = Highest drive strength

28:26

MABAHDCTL

MA/BA High Drive Control: Controls the high drive and slew rate of the memory address bus includ-

ing the memory bank address bus (MA[12:0] and BA[1:0]):

000 = Tristate

001 = Smallest drive strength

010 -110 = Represents gradual drive strength increase

111 = Highest drive strength

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