GXM datasheet(107/244 Pages) NSC

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Integrated Functions (Continued)

ACT — The activate command is used to open a row in a

particular bank for a subsequent access. The value on the

BA lines selects the bank, and the address on the MA

lines selects the row. This row remains open for accesses

until a precharge command is issued to that bank. A pre-

charge command must be issued before opening a differ-

ent row in the same bank.

READ —The read commandisusedtoinitiateaburst

read access to an active row. The value on the BA lines

select the component bank, and the address provided by

the MA lines select the starting column location. The

memory controller does not perform auto precharge dur-

ing read operations. Valid data-out from the starting col-

umn address is available following the CAS latency after

the read command. The DQM signals are asserted low

during read operations.

WRT — The write command is used to initiate a burst

writeaccess toanactiverow.The valueon the BA liens

select the component bank, and the address provided by

the MA lines select the starting column location. The

memory controller does not perform auto precharge dur-

ing write operations. This leaves the page open for subse-

quent accesses. Data appearing on the MD lines is

written to the DQM logic level appearing coincident with

the data. If the DQM signal is registered low, the corre-

sponding data will be written to memory. If the DQM is

driven high, the corresponding data will be ignored, and a

write will not be executed to that location.

REF — Auto refresh is used during normal operation and

is analogous to the CAS-before-RAS (CBR) refresh in

conventional DRAMs.During auto refresh the address bits

are "don’t care". The memory controller precharges all

banks prior to an auto refresh cycle. Auto refresh cycles

are issued approximately 15 µs apart.

The self refresh command is used to retain data in the

SDRAMs even when the rest of the system is powered

down. The self refresh command is similar to an auto

refresh command except CKE is disabled (low). The

memory controller issues a self refresh command during

3V Suspend mode when all the internal clocks are

stopped.

4.3.3.1

SDRAM Initialization Sequence

After the clocks have started and stabilized, the memory

controller SDRAM initialization sequence begins:

Precharge all component banks

Perform eight refresh cycles

Perform an MRS cycle

Perform eight refresh cycles

This sequence is compatible with the majority of SDRAMs

available from the various vendors.

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