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Revision 3.1

Integrated Functions (Continued)

4.4.6

Graphics Pipeline Register Descriptions

The graphics pipeline maps 200h locations starting at

GX_BASE+8100h. Refer to Section 4.1.2 “Control Regis-

ters” on page 94 for instructions on accessing these regis-

ters.

Table 4-24 summarizes the graphics pipeline registers

and Table 4-25 on page 125 gives detailed register/bit for-

mats.

Table 4-24. Graphics Pipeline Configuration Register Summary

GX_BASE+

Memory Offset

Type

Name / Function

Default Value

8100h-8103h

R/W

GP_DST/START_Y/XCOOR

Destination/Starting Y and X Coordinates Register — In BLT mode this register

specifies the destination Y and X positions for a BLT operation. In Vector mode it

specifies the starting Y and X positions in a vector.

00000000h

8104-8107h

R/W

GP_WIDTH/HEIGHT and GP_VECTOR_LENGTH/INIT_ERROR

Width/Height or Vector Length/Initial Error Register — In BLT mode this register

specifies the BLT width and height in pixels. In Vector mode it specifies the vector

initial error and pixel length.

00000000h

8108h-810Bh

R/W

GP_SRC_X/YCOOR and GP_AXIAL/DIAG_ERROR

Source X/Y Coordinate Axial/Diagonal Error Register — In BLT mode this register

specifies the BLT X and Y source. In Vector mode it specifies the axial and diago-

nal error for rendering a vector.

00000000h

810Ch-810Fh

R/W

GP_SRC_COLOR_0 and GP_SCR_COLOR_1

Source Color Register — Determines the colors used when expanding mono-

chrome source data in either the 8-BPP mode or the 16-BPP mode.

00000000h

8110h-8113h

R/W

GP_PAT_COLOR_0 and GP_PAT_COLOR_1

Graphics Pipeline Pattern Color 0 and 1 Registers — These two registers deter-

mine the colors used when expanding pattern data.

00000000h

8114h-8117h

R/W

GP_PAT_COLOR_2 and GP_PAT_COLOR_3

Graphics Pipeline Pattern Color 2 and 3 Registers — These two registers deter-

mine the colors used when expanding pattern data.

00000000h

8120h-8123h

R/W

GP_PAT_DATA 0 through 3

Graphics Pipeline Pattern Data Registers 0 through 3 — Together these registers

contain 128 bits of pattern data.

GP_PAT_DATA_0 corresponds to bits [31:0] of the pattern data.

GP_PAT_DATA_1 corresponds to bits [63:32] of the pattern data.

GP_PAT_DATA_2 corresponds to bits [95:64] of the pattern data.

GP_PAT_DATA_3 corresponds to bits [127:96] of the pattern data.

00000000h

8124h-8127h

R/W

00000000h

8128h-812Bh

R/W

00000000h

812Ch-812Fh

R/W

00000000h

8140h-8143h

(Note)

R/W

GP_VGA_WRITE

Graphics Pipeline VGA Write Patch Control Register — Controls the VGA mem-

ory write path in the graphics pipeline.

xxxxxxxxh

8144h-8147h

(Note)

R/W

GP_VGA_READ

Graphics Pipeline VGA Read Patch Control Register — Controls the VGA mem-

ory read path in the graphics pipeline.

00000000h

8200h-8203h

R/W

GP_RASTER_MODE

Graphics Pipeline Raster Mode Register — This register controls the manipula-

tion of the pixel data through the graphics pipeline. Refer to Section 4.4.5 “Raster

Operations” on page 123.

00000000h

8204h-8207h

R/W

GP_VECTOR_MODE

Graphics Pipeline Vector Mode Register — Writing to this register initiates the

rendering of a vector.

00000000h

8208h-820Bh

R/W

GP_BLT_MODE

Graphics Pipeline BLT Mode Register — Writing to this initiates a BLT operation.

00000000h

Note: The registers at GX_BASE+8140, 8144h, 8210h, and 8217h are located in the area designated for the graphics pipeline but

are used for VGA emulation purposes. Refer to Table 5-5 on page 173 for these register’s bit formats.

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