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Integrated Functions (Continued)

GX_BASE+820Ch-820Fh

GP_BLT_STATUS Register (R/W)

Default Value = 00000000h

31:10

RSVD

Reserved: Set to 0.

Screen Width: Selects a frame-buffer width of 2048 bytes (default is 1024 bytes).

16-BPP Mode: Selects a pixel data format of 16 BPP (default is 8 BPP).

7:3

RSVD

Reserved: Set to 0.

2BP (RO)

BLT Pending (Read Only): Indicates that a BLT operation is pending in the master registers.

The “BLT Pending” bit must be clear before loading any of the graphics pipeline registers. Loading registers

when this bit is set high will destroy the values for the pending BLT.

1PB (RO)

Pipeline Busy (Read Only): Indicates that the graphics pipeline is processing data.

The “Pipeline Busy” bit differs from the “BLT Busy” bit in that the former only indicates that the graphics pipe-

line is processing data. The “BLT Busy” bit also indicates that the memory controller has not yet processed

all of the requests for the current operation.

The “Pipeline Busy” bit must be clear before loading a BLT buffer if the previous BLT operation used the

same BLT buffer.

0BB (RO)

BLT Busy (Read Only): Indicates that a BLT / vector operation is in progress.

The “BLT Busy” bit must be clear before accessing the frame buffer directly.

GX_BASE+8210h-8213h

GP_VGA_BASE (R/W)

Default Value = xxxxxxxxh

Note that the registers at GX_BASE+8210h and 8214h are located in the area designated for the graphics pipeline but are used for

VGA emulation purposes. Refer to Table 5-5 on page 173 for these register’s bit formats.

GX_BASE+8214h-8217h

GP_VGA_LATCH Register (R/W)

Default Value = xxxxxxxxh

Note that the registers at GX_BASE+8210h and 8214h are located in the area designated for the graphics pipeline but are used for

VGA emulation purposes. Refer to Table 5-5 on page 173 for these register’s bit formats.

Table 4-25. Graphics Pipeline Configuration Registers (Continued)

Bit

Name

Description

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