GXM datasheet(131/244 Pages) NSC

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Integrated Functions (Continued)

4.5.4

Hardware Cursor

The display controller contains hardware cursor logic to

allow overlay of the cursor image onto the pixel data

stream. Overhead for updating this image on the screen is

kept to a minimum by requiring that only the X and Y posi-

tion be changed. This eliminates "submarining" effects

commonly associated with software cursors. The cursor,

32x32 pixels with two bits per pixel, is loaded into off-

screen memory within the graphics memory aperture. The

two-bit code selects color 0, color 1, transparent, or back-

ground-color inversion for each pixel in the cursor (see

Table 4-31 on page 144. The two cursor colors will be

stored as extensions to the normal 256-entry palette at

locations 100h and 101h. These palette extensions will be

used when driving a flat panel or a RAMDAC operating in

16 BPP (bits per pixel) mode. For 8 BPP operation using

an external RAMDAC, the DC_CURSOR_COLOR regis-

ter (GX_BASE+8360h) should be programmed to set the

indices for the cursor colors. To avoid corruption of the

cursor colors by an application program that modifies the

external palette, care should be taken to program the cur-

sor color indices to one of the static color indices. Since

Microsoft Windows typically uses only black and white

cursor colors and these are static colors, this kind of prob-

lem should rarely occur.

4.5.5

Display Timing Generator

The display controller features a fully programmable tim-

ing generator for generating all timing control signals for

the display. The timing control signals include horizontal

and vertical sync and blank signals in addition to timing for

active and overscan regions of the display. The timing

generator is similar in function to the CRTC of the original

VGA, although programming is more straightforward. Pro-

gramming of the timing registers will generally happen via

a BIOS INT10 call during a mode set. When programming

the timing registers directly, extreme care should be taken

to ensure that all timing is compatible with the display

device.

The timing generator supports overscan to maintain full

backward compatibility with the VGA. This feature is sup-

ported primarily for CRT display devices since flat panel

displays have fixed resolutions and do not provide for

overscan. However, the GXm processor supports a mech-

anism to center the display when a display mode is

selected having a lower resolution than the panel resolu-

tion. The border region is effectively stretched to fill the

remainder of the screen. The border color is at palette

extension 104h. For 8 BPP operation with an external

RAMDAC,

the

DC_BORDER_COLOR

(GX_BASE+8368h) should also be programmed.

4.5.6

Dither and Frame-Rate Modulation

The display controller supports 2x2 dither and two-level

frame-rate modulation (FRM) to increase the apparent

number of colors displayed on 9-bit or 12-bit TFT panels.

Dither and FRM are individually programmable. With dith-

ering and FRM enabled, 185,193 colors are possible on a

9-bit TFT panel, and 226,981 colors are possible on a 12-

bit TFT panel.

4.5.7

Display Modes

The GXm processor supports 640x480, 800x600, and

1024x768 display resolutions at both 8 and 16 bits per

pixel. In addition, 1280x1024 resolution is supported at 8

bits per pixel only. Two 16-bit display formats are sup-

ported: RGB 5-6-5 and RGB 5-5-5. All CRT modes use

VESA-compatible timing. Table 4-26 on page 132 gives

the supported CRT display modes.

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