AD9142ABCPZRL datasheet(28/73 Pages) AD

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Data Sheet

AD9142A

The autosample error detection (AED) mode is an autoclear

mode that has two effects: it activates the compare fail bit and

the compare pass bit (Register 0x60, Bit 1 and Bit 2). The

compare pass bit sets if the last comparison indicated that the

sample was error free. The compare fail bit sets if an error is

detected. The compare fail bit is automatically cleared by the

reception of eight consecutive error-free comparisons, when

autoclear mode is enabled.

The sample error flag can be configured to trigger an IRQ when

active, if needed. This is done by enabling the appropriate bit in

the event flag register (Register 4, Bit 6).

SED EXAMPLE

Normal Operation

The following example illustrates the AD9142A SED

configuration sequence for continuously monitoring the input

data and assertion of an IRQ when a single error is detected:

1. Write to the following registers to enable the SED and load

the comparison values with a 4-deep user pattern.

Comparison values can be chosen arbitrarily; however,

choosing values that require frequent bit toggling provides

the most robust test.

a. Register 0x61[7:0] → I0[7:0]

b. Register 0x62[7:0] → I0[15:8]

c. Register 0x63[7:0] → Q0[7:0]

d. Register 0x64[7:0] → Q0[15:8]

e. Register 0x65[7:0] → I1[7:0]

g. Register 0x67[7:0] → Q1[7:0]

h. Register 0x68[7:0] → Q1[15:8]

2. Enable SED.

a. Register 0x60 → 0xD0

b. Register 0x60 → 0x90

3. Enable the SED error detect flag to assert the IRQx pin.

a. Register 0x04[6] = 1

4. Set up frame parity as the frame signal.

a. Register 0x09 = 0x12

5. Begin transmitting the input data pattern (frame signal) is

also required because the depth of the pattern is 4).

DELAY LINE INTERFACE MODE

The DLL is designed to help ease the interface timing require-

ments in very high speed data rate applications. The DLL has

a minimum supported interface speed of 250 MHz, as shown

in Table 2. For interface rates lower than this speed, use the

interface delay line. In this mode, the DLL is powered off and a

four-tap delay line is provided for the user to adjust the timing

between the data bus and the DCI. Table 16 specifies the setup

and hold times for each delay tap.

Table 16. Delay Line Setup and Hold Times (Guaranteed)

Delay Setting

0x00

0x80

0xF0

0xFE

0x60

0x67

tS (ns)1

−0.81

−0.97

−1.13

−1.28

tH (ns)

1.96

2.20

2.53

2.79

|tS + tH| (ns)

1.15

1.23

1.40

1.51

The negative sign indicates the direction of the setup time. The setup time is

defined as positive when it is on the left side of the clock edge and negative

when it is on the right side of the clock edge.

There is a fixed 1.38 ns delay on the DCI signal when the delay line

is enabled. Each tap adds a nominal delay of 200 ps to the fixed

delay. To achieve the best timing margin, that is, to center the

setup and hold window in the middle of the data eye, the user

may need to add a delay on the data bus with respect to the DCI

in the data source. Figure 38 is an example of calculating the

optimal external delay.

for optimal interface performance over the operating frequency

range. It is recommended that this bit be set to 1 (dc-coupled

DCI) in the delay line interface mode.

Figure 38. Example of Interfacing Timing in the Delay Line Interface Mode

DATA EYE

NO DATA TRANSITION

INPUT DATA [15:0]

WITH OPTIMIZED DELAY

DCI = 200MHz

tDELAY = 0.63ns

tDATA PERIOD = 2.5ns

|tS| = 1.25ns

|tH| = 2.51ns

Rev. A | Page 27 of 72

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