AD9142ABCPZRL datasheet(70/73 Pages) AD

70 / 73 page

Data Sheet

AD9142A

Rev. A | Page 69 of 72

SED PATTERN Q1 HIGH BITS REGISTER

Address: 0x68, Reset: 0x00, Name: SED_PATT_H_Q1

Table 99. Bit Descriptions for SED_PATT_H_Q1

Bits

Bit Name

Description

Reset

Access

[2:0]

SED_PATTERN_FALL_Q1[15:8]

SED Q1 falling edge high bits.

0x00

PARITY CONTROL REGISTER

Address: 0x6A, Reset: 0x00, Name: PARITY_CTRL

Table 100. Bit Descriptions for PARITY_CTRL

Bits

Bit Name

Settings

Description

Reset

Access

PARITY_ENABLE

Enable parity.

PARITY_EVEN

Odd parity.

Even parity.

PARITY_ERR_CLEAR

Set to 1 to clear parity error counters.

[4:2]

Reserved

Reserved.

0x0

PARERRFAL

When 1, signals a falling edge parity error was detected.

PARERRRISE

When 1, signals a rising edge parity error was detected.

PARITY ERROR RISING EDGE REGISTER

Address: 0x6B, Reset: 0x00, Name: PARITY_ERR_RISING

Table 101. Bit Descriptions for PARITY_ERR_RISING

Bits

Bit Name

Description

Reset

Access

[7:0]

Parity Rising Edge Error Count

Number of rising edge-based errors detected (S0 and S2). Clipped

to 256.

0x00

PARITY ERROR FALLING EDGE REGISTER

Address: 0x6C, Reset: 0x00, Name: PARITY_ERR_FALLING

Table 102. Bit Descriptions for PARITY_ERR_FALLING

Bits

Bit Name

Description

Reset

Access

[7:0]

Parity Falling Edge Error Count

Number of falling edge-based errors detected (S1 and S3).

Clipped to 256.

0x00

VERSION REGISTER

Address: 0x7F, Reset: 0x0B, Name: Version

Table 103. Bit Descriptions for Version

Bits

Bit Name

Settings

Description

Reset

Access

[7:0]

Version

Chip version.

0x0B

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