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AD9142ABCPZRL 数据表(PDF) 51 Page - Analog Devices |
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AD9142ABCPZRL 数据表(HTML) 51 Page - Analog Devices |
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51 / 73 page  AD9142A Data Sheet Reg Name Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset RW 0x23 FIFO_LEVEL_ CONFIG [7:0] Reserved INTEGER_FIFO_LEVEL_REQUEST Reserved FRACTIONAL_FIFO_LEVEL_REQUEST 0x40 RW 0x24 FIFO_LEVEL_ READBACK [7:0] Reserved INTEGER_FIFO_LEVEL_READBACK Reserved FRACTIONAL_FIFO_LEVEL_READBACK 0x00 R 0x25 FIFO_CTRL [7:0] Reserved FIFO_SPI_ RESET_ACK FIFO_SPI_ RESET_ REQUEST 0x00 RW 0x26 DATA_ FORMAT [7:0] DATA_ FORMAT DATA_ PAIRING DATA_BUS_ INVERT Reserved DATA_BUS_ WIDTH 0x00 RW 0x27 DATAPATH_ CTRL [7:0] INVSINC_ ENABLE NCO_ENABLE IQ_GAIN_ADJ_ DCOFFSET_ ENABLE IQ_PHASE_ADJ_ ENABLE Reserved FS4_ MODULATION_ ENABLE NCO_ SIDEBAND_ SEL SEND_IDATA _TO_QDAC 0x00 RW 0x28 INTERPOLATION _CTRL [7:0] Reserved INTERPOLATION_MODE 0x00 RW 0x29 OVER_ THRESHOLD_ CTRL0 [7:0] THRESHOLD_LEVEL_REQUEST_LSB 0x00 RW 0x2A OVER_ THRESHOLD_ CTRL1 [7:0] Reserved THRESHOLD_LEVEL_REQUEST_MSB 0x00 RW 0x2B OVER_ THRESHOLD_ CTRL2 [7:0] ENABLE_ PROTECTION IQ_DATA_ SWAP Reserved SAMPLE_WINDOW_LENGTH 0x00 RW 0x2C INPUT_ POWER_ READBACK_LSB [7:0] INPUT_POWER_READBACK_LSB 0x00 R 0x2D INPUT_POWER_ READBACK_ MSB [7:0] Reserved INPUT_POWER_READBACK_MSB 0x00 R 0x30 NCO_CTRL [7:0] Reserved NCO_FRAME_ UPDATE_ACK SPI_NCO_ PHASE_RST_ ACK SPI_NCO_ PHASE_ RST_REQ Reserved NCO_SPI_ UPDATE_ACK NCO_SPI_ UPDATE_REQ 0x00 RW 0x31 NCO_FREQ_ TUNING_ WORD0 [7:0] NCO_FTW0 0x00 RW 0x32 NCO_FREQ_ TUNING_ WORD1 [7:0] NCO_FTW1 0x00 RW 0x33 NCO_FREQ_ TUNING_ WORD2 [7:0] NCO_FTW2 0x00 RW 0x34 NCO_FREQ_ TUNING_ WORD3 [7:0] NCO_FTW3 0x10 RW 0x35 NCO_PHASE_ OFFSET0 [7:0] NCO_PHASE_OFFSET_LSB 0x00 RW 0x36 NCO_PHASE_ OFFSET1 [7:0] NCO_PHASE_OFFSET_MSB 0x00 RW 0x37 IQ_PHASE_ ADJ0 [7:0] IQ_PHASE_ADJ_LSB 0x00 RW 0x38 IQ_PHASE_ ADJ1 [7:0] Reserved IQ_PHASE_ADJ_MSB 0x00 RW 0x39 LVDS_IN_ PWR_DOWN_0 [7:0] PWR_DOWN_DATA_INPUT_BITS 0x00 RW 0x3B IDAC_DC_ OFFSET0 [7:0] IDAC_DC_OFFSET_LSB 0x00 RW 0x3C IDAC_DC_ OFFSET1 [7:0] IDAC_DC_OFFSET_MSB 0x00 RW 0x3D QDAC_DC_ OFFSET0 [7:0] QDAC_DC_OFFSET_LSB 0x00 RW 0x3E QDAC_DC_ OFFSET1 [7:0] QDAC_DC_OFFSET_MSB 0x00 RW 0x3F IDAC_GAIN_ ADJ [7:0] Reserved IDAC_GAIN_ADJ 0x20 RW 0x40 QDAC_GAIN_ ADJ [7:0] Reserved QDAC_GAIN_ADJ 0x20 RW 0x41 GAIN_STEP_ CTRL0 Reserved RAMP_UP_STEP 0x01 RW Rev. A | Page 50 of 72 |
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