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AD9142ABCPZRL 数据表(PDF) 66 Page - Analog Devices |
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AD9142ABCPZRL 数据表(HTML) 66 Page - Analog Devices |
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66 / 73 page  Data Sheet AD9142A POWER DOWN DATA INPUT 0 REGISTER Address: 0x39, Reset: 0x00, Name: LVDS_IN_PWR_DOWN_0 Table 78. Bit Descriptions for LVDS_IN_PWR_DOWN_0 Bits Bit Name Settings Description Reset Access [3:0] PWR_DOWN_DATA_INPUT_BITS Powers down data input D[3:0]. Each bit controls one data input bit. These bits can be powered down individually. 0x0 RW IDAC DC OFFSET 0 REGISTER Address: 0x3B, Reset: 0x00, Name: IDAC_DC_OFFSET0 Table 79. Bit Descriptions for IDAC_DC_OFFSET0 Bits Bit Name Settings Description Reset Access [7:0] IDAC_DC_OFFSET_LSB DAC dc offset, Bits[7:0] along with Bits[7:0] in Register 0x3C, is a dc value that is added directly to the sample values written to the DAC. 0x00 RW IDAC DC OFFSET 1 REGISTER Address: 0x3C, Reset: 0x00, Name: IDAC_DC_OFFSET1 Table 80. Bit Descriptions for IDAC_DC_OFFSET1 Bits Bit Name Settings Description Reset Access [7:0] IDAC_DC_OFFSET_MSB DAC dc offset, Bits[7:0] along with Bits[7:0] in Register 0x3B, is a dc value that is added directly to the sample values written to the DAC. 0x00 RW QDAC DC OFFSET 0 REGISTER Address: 0x3D, Reset: 0x00, Name: QDAC_DC_OFFSET0 Table 81. Bit Descriptions for QDAC_DC_OFFSET0 Bits Bit Name Settings Description Reset Access [7:0] QDAC_DC_OFFSET_LSB QDAC dc offset, Bits[7:0] along with Bits[7:0] in Register 0x3E, is a dc value that is added directly to the sample values written to the QDAC. 0x00 RW QDAC DC OFFSET 1 REGISTER Address: 0x3E, Reset: 0x00, Name: QDAC_DC_OFFSET1 Table 82. Bit Descriptions for QDAC_DC_OFFSET1 Bits Bit Name Settings Description Reset Access [7:0] QDAC_DC_OFFSET_MSB QDAC dc offset, Bits[7:0] along with Bits[7:0] in Register 0x3D, is a dc value that is added directly to the sample values written to the QDAC. 0x00 RW IDAC GAIN ADJUST REGISTER Address: 0x3F, Reset: 0x20, Name: IDAC_GAIN_ADJ Table 83. Bit Descriptions for IDAC_GAIN_ADJ Bits Bit Name Settings Description Reset Access [5:0] IDAC_GAIN_ADJ This register is the 6-bit digital gain adjust on the I channel.The bit weighting is MSB = 20, LSB = 2−5, which yields a multiplier range of 0 to 2 or −∞ to 6 dB.The default gain setting is 0x20, which maps to unity gain (0 dB). 0x20 RW Rev. A | Page 65 of 72 |
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