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AD9142ABCPZRL 数据表(PDF) 9 Page - Analog Devices

部件名 AD9142ABCPZRL
功能描述  Multiple chip synchronization
PDF  73 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD9142ABCPZRL 数据表(HTML) 9 Page - Analog Devices

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AD9142A
Data Sheet
DIGITAL SPECIFICATIONS
TMIN to TMAX, AVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFS = 20 mA, maximum sample rate, unless otherwise noted.
Table 2.
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
CMOS INPUT LOGIC LEVEL
Input
Logic High
DVDD18 = 1.8 V
1.2
V
Logic Low
DVDD18 = 1.8 V
0.6
V
CMOS OUTPUT LOGIC LEVEL
Output
Logic High
DVDD18 = 1.8 V
1.4
V
Logic Low
DVDD18 = 1.8 V
0.4
V
LVDS RECEIVER INPUTS
Data, frame signal, and DCI inputs
Input Voltage Range
VIA or VIB
825
1675
mV
Input Differential Threshold
VIDTH
−175
+175
mV
Input Differential Hysteresis
VIDTHH to VIDTHL
20
mV
Receiver Differential Input Impedance
RIN
100
Ω
DLL SPEED RANGE
250
575
MHz
DAC UPDATE RATE
1600
MSPS
DAC Adjusted Update Rate
2× interpolation
575
MSPS
DAC CLOCK INPUT (DACCLKP, DACCLKN)
Differential Peak-to-Peak Voltage
100
500
2000
mV
Common-Mode Voltage
Self biased input, ac-coupled
1.25
V
REFCLK/SYNCCLK INPUT (REFP/SYNCP, REFN/SYNCN)
Differential Peak-to-Peak Voltage
100
500
2000
mV
Common-Mode Voltage
1.25
V
Input Clock Frequency
1.03 GHz ≤ fVCO ≤ 2.07 GHz
450
MHz
SERIAL PORT INTERFACE
Maximum Clock Rate
SCLK
40
MHz
Minimum Pulse Width
High
tPWH
12.5
ns
Low
tPWL
12.5
ns
SDIO to SCLK Setup Time
tDS
1.5
ns
SDIO to SCLK Hold Time
tDH
0.68
ns
CS to SCLK Setup Time
tDCSB
2.38
1.4
ns
CS to SCLK Hold Time
tDCSB
9.6
ns
SDIO to SCLK Delay
tDV
Wait time for valid output from
SDIO
11
ns
SDIO High-Z to CS
Time for SDIO to relinquish the
output bus
8.5
ns
SDIO LOGIC LEVEL
Voltage Input High
VIH
1.2
1.8
V
Voltage Input Low
VIL
0
0.5
V
Voltage Output High
IIH
With 2 mA loading
1.36
2
V
Voltage Output Low
IIL
With 2 mA loading
0
0.45
V
Rev. A | Page 8 of 72



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