AD9142ABCPZRL datasheet(72/73 Pages) AD

72 / 73 page

Data Sheet

AD9142A

Rev. A | Page 71 of 72

CLOCK GENERATION LATENCY VARIATION

The state machine of the clock generation circuitry is another

source of latency variations; this type of latency variation results

from inherent phase uncertainty of the static frequency dividers.

The divided down clock can be high or low at the rising edge of

the input clock, unless specifically forced to a known state. This

means that whenever there is interpolation (when slower clocks

must be internally generated by dividing down the DACCLK),

there is an inherent latency variation in the DAC. Figure 65 is an

example of this latency variation in 2× interpolation.

There are two phase possibilities in the DACCLK/2 clock. The

DACCLK/2 clock is used to read data from the FIFO and to drive

the interpolation filter. Regardless of which clock edge is used to

drive the digital circuit, there is a latency of one DAC clock cycle

between Case 1 and Case 2 (see Figure 65). Because the power-

on state arbitrarily falls in one of the two cases, the phase

uncertainty of the divider appears as a varying skew between two

DAC outputs.

Figure 65. Latency Variation in 2× Interpolation from Clock Generation

CORRECTING SYSTEM SKEWS

Generally, it is assumed that the input data and the DCI among

multiple devices are well aligned to each other. Depending on the

system design, the data and DCI being input into each DAC can

originate from various FPGAs or ASICs. Without synchronizing

the data sources, the output of one data source can be skewed

from that of another. The alignment between multiple data

sources can also drift over temperature.

Figure 66 shows an example of a 2-channel transmitter with two

data sources and two dual DACs. A constant but unknown phase

offset appears between the outputs of the DAC devices, even if

the DAC does not introduce any latency variations. The

multidevice synchronization in the AD9142A can be used to

compensate the skew due to misalignment of the data sources by

resetting the two sides of the FIFO independently through two

external reference clocks: the frame and the sync clock. The offset

between the two data sources is then absorbed by the FIFO and

clock generation block in the DAC. For more information about

using the multidevice synchronization function, refer to the

Synchronization Implementation section.

Figure 66. DAC Output Skew from Skewed Input Data and DCI

HB1

HB2

HB3

DACCLK

DACCLK/2

(CASE 1)

DACCLK/2

(CASE 2)

LATENCY VARIATION = 1 DACCLK CYCLE

DAC

16-BIT DATA

FRAME

DCI

16-BIT DATA

FRAME

DCI

16-BIT DATA

FRAME

DCI

16-BIT DATA

FRAME

SYNC CLOCK

DATA SKEW

DATA

GEN

DATA

GEN

MASTER

REF CLOCK

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