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AD9142ABCPZRL 数据表(PDF) 58 Page - Analog Devices |
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AD9142ABCPZRL 数据表(HTML) 58 Page - Analog Devices |
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58 / 73 page  Data Sheet AD9142A PLL CONTROL 2 REGISTER Address: 0x14, Reset: 0xE7, Name: PLL_CTRL2 Table 43. Bit Descriptions for PLL_CTRL2 Bits Bit Name Settings Description Reset Access [7:5] PLL_LOOP_BW Selects the PLL filter bandwidth. The default and recommended setting is 111 for optimal PLL performance. 0x7 RW 0x00 Lowest setting. 0x1F Highest setting. [4:0] PLL_CP_CURRENT Sets nominal PLL charge pump current. The default and recommended setting is 00111 for optimal PLL performance. 0x07 RW 0x00 Lowest setting. 0x1F Highest setting. PLL CONTROL 3 REGISTER Address: 0x15, Reset: 0xC9, Name: PLL_CTRL3 Table 44. Bit Descriptions for PLL_CTRL3 Bits Bit Name Settings Description Reset Access [7:6] DIGLOGIC_DIVIDER REFCLK to PLL digital clock divide ratio. The PLL digital clock drives the internal PLL logics. The divide ratio must be set to ensure that the PLL digital clock is less than 75 MHz. 0x3 RW 00 fREFCLK/fDIG = 2. 01 fREFCLK/fDIG = 4. 10 fREFCLK/fDIG = 8. 11 fREFCLK/fDIG = 16. 4 CROSSPOINT_CTRL_EN Enable loop divider crosspoint control. The default and recommended setting is set to 0 for optimal PLL performance. 0 RW [3:2] VCO_DIVIDER PLL VCO divider. This divider determines the ratio of the VCO frequency to the DACCLK frequency. 0x2 RW 00 fVCO/fDACCLK = 1. 01 fVCO/fDACCLK = 2. 10 fVCO/fDACCLK = 4. 11 fVCO/fDACCLK = 4. [1:0] LOOP_DIVIDER PLL divider. This divider determines the ratio of the DACCLK frequency to the REFCLK frequency. 0x1 RW 00 fDACCLK/fREFCLK = 2. 01 fDACCLK/fREFCLK = 4. 10 fDACCLK/fREFCLK = 8. 11 fDACCLK/fREFCLK = 16. PLL STATUS 0 REGISTER Address: 0x16, Reset: 0x00, Name: PLL_STATUS0 Table 45. Bit Descriptions for PLL_STATUS0 Bits Bit Name Settings Description Reset Access 7 PLL_LOCK PLL clock multiplier output is stable. 0 R [3:0] VCO_CTRL_VOLTAGE_READBACK VCO control voltage readback. A binary value. 0x0 R 1111 The highest VCO control voltage. 0111 The midvalue when a proper VCO band is selected. When the PLL is locked, selecting a higher VCO band decreases this value and selecting a lower VCO band increases this value. 0000 The lowest VCO control voltage. Rev. A | Page 57 of 72 |
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