AD9142ABCPZRL datasheet(48/73 Pages) AD

48 / 73 page

Data Sheet

AD9142A

EXAMPLE START-UP ROUTINE

To ensure reliable startup of the AD9142A, certain sequences

must be followed.

DEVICE CONFIGURATION AND START-UP

SEQUENCE 1

1. Set fDCI = 375 MHz, fOUT = 250 MHz, and interpolation to 4×.

2. Disable the PLL.

3. Enable fine NCO and the inverse sinc filter.

4. Use the DLL-based interface mode with DLL phase offset = 0.

Derived NCO Settings

The following NCO settings can be derived from the device

configuration:

•

fDAC = 375 × 4 = 1500 MHz.

•

fCARRIER = fOUT = 250 MHz.

•

FTW = fCARRIER/fDAC × 232 = 0x2AAAAAAA.

Start-Up Sequence 1

1. Power up the device (no specific power supply sequence is

required).

2. Apply stable DAC clock.

3. Apply stable DCI clock.

4. Feed stable input data.

5. Issue hardware reset (optional).

/* Device configuration register write sequence

0x00 → 0x20 /* Issue software reset */

0x20 → 0x01 /* Device startup configuration */

/* Configure data interface */

0x5E → 0xFE /* Turn off LSB delay cell */

0x0A → 0xC0 /* Enable the DLL and duty cycle

correction. Set DLL phase offset to 0 */

Read 0x0E[7:4] /* Expect 1000b if the DLL is

locked */

/* Configure interpolation filter */

0x28 → 0x02 /* 4× interpolation */

/* Reset FIFO */

0x25 → 0x01

Read 0x25[1] /* Expect 1b if the FIFO reset is

complete */

Read 0x24 /* The readback should be one of the

three values: 0x33, 0x40, or 0x41 */

/* Configure NCO */

0x27→ 0x40 /* Enable NCO */

0x31 → 0xAA

0x32 → 0xAA

0x33 → 0xAA

0x34 → 0x2A

0x30 → 0x01

Read 0x30[1] /* Expect 1b if the NCO update is

complete */

/* Enable inverse sinc filter */

0x27 → 0xC0

/* Power up DAC outputs */

0x01 → 0x00

DEVICE CONFIGURATION AND START-UP

SEQUENCE 2

1. Set fDCI = 200 MHz and interpolation to 8×.

2. Enable the PLL, and set fREF = 200 MHz.

3. Enable the inverse sinc filter.

4. Use the delay line-based interface mode with a delay

setting of 0.

Derived PLL Settings

The following PLL settings can be derived from the device

configuration:

•

fDAC = 200 × 8 = 1600 MHz.

•

fVCO= fDAC = 1600 MHz (1.03 GHz < fVCO < 2.07 GHz).

•

VCO divider = fVCO/fDAC = 1.

•

Loop divider = fDAC/fREF = 8.

Start-Up Sequence 2

1. Power up the device (no specific power supply sequence is

required).

2. Apply stable DAC clock.

3. Apply stable DCI clock.

4. Feed stable input data.

5. Issue hardware reset (optional).

/* Device configuration register write sequence

0x00 → 0x20 /* Issue software reset */

0x20 → 0x01 /* Device startup configuration */

/* Configure PLL */

0x14 → 0xE7 /* Configure PLL loop BW and charge

pump current */

0x15 → 0xC2 /* Configure VCO divider and loop

divider */

0x12 → 0xC0 /*Enable the PLL */

0x12 → 0x80

Wait 10ms for autoband selection to finish

Read 0x16[7] /* Expect 1b if the PLL is locked

Rev. A | Page 47 of 72

AD9142ABCPZRL 数据表(PDF) 48 Page - Analog Devices

AD9142ABCPZRL 数据表(HTML) 48 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73

数据表下载