AD9142ABCPZRL datasheet(44/73 Pages) AD

44 / 73 page

Data Sheet

AD9142A

PLL SETTINGS

The PLL circuitry requires three settings to be programmed to

their nominal values. The PLL values shown in Table 24 are the

recommended settings for these parameters.

Table 24. PLL Settings

PLL SPI Control Register

Address

Optimal Setting

(Binary)

PLL Loop Bandwidth

0x14[7:5]

111

PLL Charge Pump Current

0x14[4:0]

00111

PLL Cross Point Control Enable

0x15[4]

CONFIGURING THE VCO TUNING BAND

The PLL VCO has a valid operating range from approximately

1.03 GHz to 2.07 GHz covered in 64 overlapping frequency

bands. For any desired VCO output frequency, there may be

several valid PLL band select values. The frequency bands of a

typical device are shown in Figure 55. Device-to-device

variations and operating temperature affect the actual band

frequency range. Therefore, it is required that the optimal PLL

band select value be determined for each individual device.

AUTOMATIC VCO BAND SELECT

The device has an automatic VCO band select feature on chip.

Using the automatic VCO band select feature is a simple and

reliable method of configuring the VCO frequency band. This

feature is enabled by starting the PLL in manual mode, and then

placing the PLL in autoband select mode by setting Register 0x12

to a value of 0xC0 and then to a value of 0x80. When these

values are written, the device executes an automated routine

that determines the optimal VCO band setting for the device.

The setting selected by the device ensures that the PLL remains

locked over the full −40°C to +85°C operating temperature

range of the device without further adjustment. The PLL

remains locked over the full temperature range even if the

temperature during initialization is at one of the temperature

extremes.

Figure 55. PLL Lock Range for a Typical Device

MANUAL VCO BAND SELECT

The device includes a manual band select mode (PLL auto

manual enable, Register 0x12[6] = 1) that lets the user select the

VCO tuning band. In manual mode, the VCO band is set

directly with the value written to the manual VCO band bits

(Register 0x12[5:0]).

PLL ENABLE SEQUENCE

To enable the PLL in automatic or manual mode properly, the

following sequence must be followed:

Automatic Mode Sequence

4. Configure the loop divider and the VCO divider registers

for the desired divide ratios.

5. Set 00111b to PLL charge pump current and 111b to PLL loop

bandwidth for the best performance. Register 0x14 = 0xE7

(default).

6. Set the PLL mode to manual using Register 0x12[6] = 1.

7. Enable the PLL using Register 0x12[7] = 1.

8. Set the PLL mode to automatic using Register 0x12[6] = 0.

Manual Mode

1. Configure the loop divider and the VCO divider registers

for the desired divide ratios.

2. Set 00111b to PLL charge pump current and 111 to PLL loop

bandwidth for the best performance. Register 0x14 = 0xE7

(default).

3. Select the desired band using Register 0x12[5:0].

4. Set the PLL mode to manual using Register 0x12[6] = 1.

5. Enable the PLL using Register 0x12[7] = 1.

950

1150

1350

1550

1750

1950

2150

VCO FREQUENCY (MHz)

Rev. A | Page 43 of 72

AD9142ABCPZRL 数据表(PDF) 44 Page - Analog Devices

AD9142ABCPZRL 数据表(HTML) 44 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73

数据表下载