AD9142ABCPZRL datasheet(37/73 Pages) AD

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AD9142A

Data Sheet

Rev. A | Page 36 of 72

INVERSE SINC FILTER

The AD9142A provides a digital inverse sinc filter to

compensate for the DAC roll-off over frequency. The inverse sinc

(sinc−1) filter is a seven-tap FIR filter. Figure 49 shows the

frequency response of sin(x)/x roll-off, the inverse sinc filter,

and their composite response. The composite response has less

than ±0.05 dB pass-band ripple up to a frequency of 0.4 × fDAC.

To provide the necessary peaking at the upper end of the pass

band, the inverse sinc filter has an intrinsic insertion loss of about

3.8 dB. The loss of the digital gain can be offset by increasing the

quadrature gain adjustment setting on both the I and Q data paths

to minimize the impact on the output signal-to-noise ratio. How-

ever, care is needed to ensure that the additional digital gain does

not cause signal saturation, especially at high output frequencies.

The sinc−1 filter is disabled by default; it can be enabled by setting

the INVSINC_ENABLE bit to 1 in Register 0x27[7]).

Figure 49. Responses of sin(x)/x Roll Off (Blue), the Sinc−1 Filter (Red), and

Composite of Both (Black)

Table 21. Inverse Sinc Filter

Lower Coefficient

Upper Coefficient

Integer Value

H(1)

H(7)

−1

H(2)

H(6)

H(3)

H(5)

−16

H(4)

+192

INPUT SIGNAL POWER DETECTION AND

PROTECTION

The input signal power detection and protection function detects

the average power of the DAC input signal and prevents overrange

signals from being passed to the next stage. An overrange DAC

output signal can cause destructive breakdown on power sensitive

devices, such as power amplifiers. The power detection and

protection feature of the AD9142A detects overrange signals in

the DAC. When an overrange signal is detected, the protection

function either attenuates or mutes the signal to protect the

downstream devices from abnormal power surges in the signal.

Figure 50 shows the block diagram of the power detection and

protection function. The protection block is at the very last stage of

the data path and the detection block uses a separate path from

the data path. The design of the detection block guarantees that

the worst-case latency of power detecting is shorter than that of

the data path. This ensures that the protection circuit initiates

before the overrange signal reaches the analog DAC core.

The sum of I2 and Q2 is calculated as a representation of the

input signal power. Only the upper six MSBs, D[15:10], of data

samples are used in the calculation; consequently, samples whose

power is 36 dB below the full-scale peak power are not detected.

The calculated sample power numbers accumulate through a

moving average filter. Its output is the average of the input

signal power in a certain number of data clock cycles. The length

of the filter is configurable through the

SAMPLE_WINDOW_LENGTH (Register 0x2B[3:0]). To

determine whether the input average power is over range,

the device averages the power of the samples in the filter

and compares the average power with a user defined

threshold, THRESHOLD_LEVEL_REQUEST_LSB and

THRESHOLD_LEVEL_REQUEST_MSB (Register 0x29[7:0]

and Register 0x2A[4:0]). When the output of the averaging filter

is larger than the threshold, the DAC output is either attenuated or

muted.

The appropriate filter length and average power threshold for

effective protection are application dependent. It is recommended

that experiments be performed with real-world vectors to

determine the values of these parameters.

Figure 50. Block Diagram of Input Signal Power Detection and Protection Function

–5

–4

–3

–2

–1

0.05

0.10

0.15

0.20

0.25

0.30

0.35

0.40

0.50

0.45

FREQUENCY (Hz)

AVERAGING

FILTER

SIGNAL

PROCESSING

ENGINE

POWER

PROTECTION

(ATTENUATE

OR MUTE)

DAC

CORE

FILTER LENGTH

SETTINGS

REG 0x2B[3:0]

USER DEFINED THRESHOLD

REG 0x29[7:0] AND

REG 0x2A[4:0]

AVG POWER

REG 0x2C[7:0] AND

REG 0x2D[4:0]

POWER DETECTION

FIFO

I2 + Q2

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