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AD9142ABCPZRL 数据表(PDF) 46 Page - Analog Devices

部件名 AD9142ABCPZRL
功能描述  Multiple chip synchronization
PDF  73 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD9142ABCPZRL 数据表(HTML) 46 Page - Analog Devices

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Data Sheet
AD9142A
Rev. A | Page 45 of 72
Figure 58 shows the most basic DAC output circuitry. A pair of
resistors, RO, converts each of the complementary output currents
to a differential voltage output, VOUT. Because the current
outputs of the DAC are high impedance, the differential driving
point impedance of the DAC outputs, ROUT, is equal to 2 × RO.
See Figure 59 for the output voltage waveforms.
Figure 58. Basic Transmit DAC Output Circuit
Figure 59. Output Voltage Waveforms
The common-mode signal voltage, VCM, is calculated as
O
FS
CM
R
I
V
2
The peak output voltage, VPEAK, is calculated as
VPEAK = IFS × RO
In this circuit configuration, the single-ended peak voltage is
the same as the peak differential output voltage.
INTERFACING TO MODULATORS
The AD9142A interfaces to the ADL537x family of modulators
with a minimal number of components. An example of the
recommended interface circuitry is shown in Figure 60.
Figure 60. Typical Interface Circuitry Between the AD9142A and the ADL537x
Family of Modulators
The baseband inputs of the ADL537x family require a dc bias
of 500 mV. The nominal midscale output current on each output of
the DAC is 10 mA (one-half the full-scale current). Therefore,
a single 50 Ω resistor to ground from each of the DAC outputs
results in the desired 500 mV dc common-mode bias for the
inputs to the ADL537x. The addition of the load resistor in
parallel with the modulator inputs reduces the signal level. The
peak-to-peak voltage swing of the transmitted signal is
)
2
(
)
2
(
L
B
L
B
FS
SIGNAL
R
R
R
R
I
V
Baseband Filter Implementation
Most applications require a baseband anti-imaging filter between
the DAC and the modulator to filter out Nyquist images and
broadband DAC noise. The filter can be inserted between the
I-V resistors at the DAC output and the signal level setting resistor
across the modulator input. This configuration establishes the
input and output impedances for the filter.
Figure 61 shows a fifth-order, low-pass filter. A common-mode
choke is placed between the I-V resistors and the remainder of
the filter to remove the common-mode signal produced by the
DAC and to prevent the common-mode signal from being
converted to a differential signal, which can appear as unwanted
spurious signals in the output spectrum. Splitting the first filter
capacitor into two and grounding the center point creates a
common-mode low-pass filter, which provides additional
common-mode rejection of high frequency signals. A purely
differential filter can pass common-mode signals.
For more details about interfacing the AD9142A DAC to an
IQ modulator, refer to the Circuits from the Lab™ Circuit Note
CN-0205, Interfacing the ADL5375 I/Q Modulator to the AD9122
Dual Channel, 1.2 GSPS High Speed DAC on the Analog Devices
website.
Figure 61. DAC Modulator Interface with Fifth-Order, Low-Pass Filter
RO
RO
VIP +
VIN
VOUTI
IOUT1P
IOUT1N
RO
RO
VQP +
VQN
VOUTQ
IOUT2P
IOUT2N
+VPEAK
VCM
0
–VPEAK
VN
VP
VOUT
RBIP
50Ω
RBIN
50Ω
67
66
IBBN
IBBP
AD9142A
ADL537x
RBQN
50Ω
RBQP
50Ω
59
58
RLI
100Ω
RLQ
100Ω
IOUT1N
IOUT1P
IOUT2P
IOUT2N
QBBP
QBBN
AD9142A
50Ω
50Ω
33nH
33nH
3.6pF
33nH
33nH
140Ω
6pF
3pF
3pF
22pF
22pF
ADL537x



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