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AD9142ABCPZRL 数据表(PDF) 49 Page - Analog Devices

部件名 AD9142ABCPZRL
功能描述  Multiple chip synchronization
PDF  73 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD9142ABCPZRL 数据表(HTML) 49 Page - Analog Devices

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AD9142A
Data Sheet
/* Configure data interface */
0x5E → 0x00 /* Configure the delay setting */
0x5F → 0x60
0x0D → 0x16 /* DC couple DCI */
0x0A → 0x00 /* Turn off DLL and duty cycle
correction */
/* Configure interpolation filter */
0x28 → 0x03 /* 8× interpolation */
/* Reset FIFO */
0x25 → 0x01
Read 0x25[1] /* Expect 1b if the FIFO reset is
complete */
Read 0x24 /* The readback should be one of the
three values: 0x37, 0x40, or 0x41 */
/* Enable inverse sinc filter */
0x27 → 0x80
/* Power up DAC outputs */
0x01 → 0x00
Rev. A | Page 48 of 72



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