 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
AD9142ABCPZRL 数据表(PDF) 62 Page - Analog Devices |
|
|
|||||||||||||||||||||||||||||
AD9142ABCPZRL 数据表(HTML) 62 Page - Analog Devices |
|
|
62 / 73 page  Data Sheet AD9142A FIFO LEVEL READBACK REGISTER Address: 0x24, Reset: 0x00, Name: FIFO_LEVEL_READBACK Table 59. Bit Descriptions for FIFO_LEVEL_READBACK Bits Bit Name Settings Description Reset Access [6:4] INTEGER_FIFO_LEVEL_READBACK The integer FIFO level read back. The difference between the overall FIFO level request and readback should be within two DACCLK cycles. See the FIFO Operation section for details. 0x0 R [2:0] FRACTIONAL_FIFO_LEVEL_READBACK The fractional FIFO level read back. This value should be used in combination with the readback in Bits[6:4]. 0x0 R FIFO CONTROL REGISTER Address: 0x25, Reset: 0x00, Name: FIFO_CTRL Table 60. Bit Descriptions for FIFO_CTRL Bits Bit Name Settings Description Reset Access 1 FIFO_SPI_RESET_ACK Acknowledge a serial port initialized FIFO reset. 0x0 R 0 FIFO_SPI_RESET_REQUEST Initialize a FIFO reset via the serial port. 0x0 RW DATA FORMAT SELECT REGISTER Address: 0x26, Reset: 0x00, Name: DATA_FORMAT_SEL Table 61. Bit Descriptions for DATA_FORMAT_SEL Bits Bit Name Settings Description Reset Access 7 DATA_FORMAT Select binary or twos complement data format. 0x0 RW 0 Input data in twos complement format. 1 Input data in binary format. 6 DATA_PAIRING Indicate I/Q data pairing on data input. 0x0 RW 0 I samples are paired with the next Q samples. 1 I samples are paired with the prior Q samples. 5 DATA_BUS_INVERT Swap the bit order of the data input port. MSBs become the LSBs: D[15:0] changes to D[0:15]. 0x0 RW 0 The order of the data bits corresponds to the pin descriptions in Table 9. 1 The order of the data bits is inverted. 0 DATA_BUS_WIDTH Data interface mode. See the LVDS Input Data Ports section for information about the operation of the different interface modes. 0x0 RW 0 Word interface mode; 16-bit interface bus width. 1 Byte interface mode; 8-bit interface bus width. DATAPATH CONTROL REGISTER Address: 0x27, Reset: 0x00, Name: DATAPATH_CTRL Table 62. Bit Descriptions for DATAPATH_CTRL Bits Bit Name Settings Description Reset Access 7 INVSINC_ENABLE Enable the inverse sinc filter. 0x0 RW 6 NCO_ENABLE Enable the NCO. 0x0 RW 5 IQ_GAIN_ADJ_DCOFFSET_ENABLE Enable digital IQ gain adjustment and dc offset. 0x0 RW 4 IQ_PHASE_ADJ_ENABLE Enable digital IQ phase adjustment. 0x0 RW 2 FS4_MODULATION_ENABLE Enable fS/4 modulation function. 0x0 RW 1 NCO_SIDEBAND_SEL Selects the single-side NCO modulation image. 0x0 RW 0 The NCO outputs the high-side image. 1 The NCO outputs the low-side image. 0 SEND_IDATA_TO_QDAC Send the IDATA to the QDAC. When enabled, I data is sent to both the IDAC and the QDAC. The Q data path still runs, and the Q data is ignored. 0x0 RW Rev. A | Page 61 of 72 |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
