AD9142ABCPZRL datasheet(61/73 Pages) AD

61 / 73 page

AD9142A

Data Sheet

SYNC CONTROL REGISTER

Address: 0x21, Reset: 0x00, Name: SYNC_CTRL

Table 56. Bit Descriptions for SYNC_CTRL

Bits

Bit Name

Settings

Description

Reset

Access

SYNC_CLK_EDGE_SEL

Selects the sampling edge of the DACCLK on the sync clock.

SYNC CLK is sampled by the falling edges of DACCLK.

SYNC CLK is sampled by the rising edges of DACCLK.

SYNC_ENABLE

Enables multichip synchronization.

FRAME RESET CONTROL REGISTER

Address: 0x22, Reset: 0x12, Name: FRAME_RST_CTRL

Table 57. Bit Descriptions for FRAME_RST_CTRL

Bits

Bit Name

Settings

Description

Reset

Access

ARM_FRAME

This bit is used to retrigger a frame reset in one shot mode (when Bit

2 is set to 0). Setting this bit to 1 requests the device to respond to

the next valid frame pulse.

EN_CON_FRAME_RESET

Frame reset mode selection.

Responds to the first valid frame pulse and resets the FIFO one time

only. This is the default and recommended mode.

Responds to every valid frame pulse and resets the FIFO

continuously.

[1:0]

FRAME_RESET_MODE

These bits determine what is to be reset when the device receives a

valid frame signal.

0x2

FIFO only.

NCO only.

FIFO and NCO.

None.

FIFO LEVEL CONFIGURATION REGISTER

Address: 0x23, Reset: 0x40, Name: FIFO_LEVEL_CONFIG

Table 58. Bit Descriptions for FIFO_LEVEL_CONFIG

Bits

Bit Name

Settings

Description

Reset

Access

[6:4]

INTEGER_FIFO_LEVEL_REQUEST

These bits set the integer FIFO level. This is the difference

between the read pointer and the write pointer values in

the unit of input data rate (fDATA). The default and

recommended FIFO level is integer level = 4 and fractional

level = 0. See the FIFO Operation section for details.

0x4

000

001

…

111

[2:0]

FRACTIONAL_FIFO_LEVEL_REQUEST

Set the fractional FIFO level. This is the difference between

the read pointer and the write pointer values in the unit of

DACCLK rate (fDAC). The maximum allowed setting value =

interpolation rate − 1. See the FIFO Operation section for

details.

0x0

000

001

Rev. A | Page 60 of 72

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