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AD9142ABCPZRL 数据表(PDF) 13 Page - Analog Devices |
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AD9142ABCPZRL 数据表(HTML) 13 Page - Analog Devices |
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13 / 73 page ![]() AD9142A Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 2. Pin Configuration Table 9. Pin Function Descriptions Pin No. Mnemonic Description 1 CVDD18 1.8 V PLL Supply. CVDD18 supplies the clock receivers, clock multiplier, and clock distribution. 2 REFP/SYNCP PLL Reference Clock/Synchronization Clock Input, Positive. 3 REFN/SYNCN PLL Reference Clock/Synchronization Clock Input, Negative. 4 CVDD18 1.8 V PLL Supply. CVDD18 supplies the clock receivers, clock multiplier, and clock distribution. 5 RESET Reset, Active Low. CMOS levels with respect to DVDD18. Recommended reset pulse length is 1 µs. 6 TXEN Active High Transmit Path Enable. CMOS levels with respect to DVDD18. A low level on this pin triggers three selectable actions in the DAC. See Table 87 for details. 7 DVDD18 1.8 V Digital Supply. Pin 7 supplies power to the digital core, digital data ports, serial port input/output pins, RESET, IRQ1, and IRQ2. 8 FRAMEP/PARITYP Frame/Parity Input, Positive. 9 FRAMEN/PARITYN Frame/Parity Input, Negative. 10 D15P Data Bit 15 (MSB), Positive. 11 D15N Data Bit 15 (MSB), Negative. 12 DVDD18 1.8 V Digital Supply. Pin 12 supplies the power to the digital core and digital data ports, serial port input/output pins, RESET, IRQ1, and IRQ2. 13 D14P Data Bit 14, Positive. 14 D14N Data Bit 14, Negative. 15 D13P Data Bit 13, Positive. 16 D13N Data Bit 13, Negative. 17 D12P Data Bit 12, Positive. 18 D12N Data Bit 12, Negative. 19 DVDD18 1.8 V Digital Supply. Pin 19 supplies power to the digital core, digital data ports, serial port input/output pins, RESET, IRQ1, and IRQ2. 20 D11P Data Bit 11, Positive. 21 D11N Data Bit 11, Negative. 22 D10P Data Bit 10, Positive. 23 D10N Data Bit 10, Negative. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CVDD18 REFP/SYNCP REFN/SYNCN CVDD18 RESET TXEN DVDD18 FRAMEP/PARITYP FRAMEN/PARITYN D15P D15N DVDD18 D14P D14N D13P D13N 17 D12P 18 D12N 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 CS SCLK SDIO IRQ1 IRQ2 DVDD18 DVDD18 D0N D0P D1N D1P DVDD18 D2N D2P D3N D3P D4N D4P AD9142A TOP VIEW (Not to Scale) NOTES 1. EXPOSED PAD (EPAD) MUST BE SOLDERED TO THE GROUND PLANE (AVSS, DVSS, CVSS). THE EPAD PROVIDES AN ELECTRI- CAL, THERMAL, AND MECHANICAL CONNECTION TO THE BOARD. Rev. A | Page 12 of 72 |
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