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AD9142ABCPZRL 数据表(PDF) 69 Page - Analog Devices |
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AD9142ABCPZRL 数据表(HTML) 69 Page - Analog Devices |
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69 / 73 page  AD9142A Data Sheet SED PATTERN I0 LOW BITS REGISTER Address: 0x61, Reset: 0x00, Name: SED_PATT_L_I0 Table 92. Bit Descriptions for SED_PATT_L_I0 Bits Bit Name Description Reset Access [7:0] SED_PATTERN_RISE_I0[7:0] SED I0 rising edge low bits. 0x00 RW SED PATTERN I0 HIGH BITS REGISTER Address: 0x62, Reset: 0x00, Name: SED_PATT_H_I0 Table 93. Bit Descriptions for SED_PATT_H_I0 Bits Bit Name Description Reset Access [7:0] SED_PATTERN_RISE_I0[15:8] SED I0 rising edge high bits. 0x00 RW SED PATTERN Q0 LOW BITS REGISTER Address: 0x63, Reset: 0x00, Name: SED_PATT_L_Q0 Table 94. Bit Descriptions for SED_PATT_L_Q0 Bits Bit Name Description Reset Access [7:0] SED_PATTERN_FALL_Q0[7:0] SED Q0 falling edge low bits. 0x00 RW SED PATTERN Q0 HIGH BITS REGISTER Address: 0x64, Reset: 0x00, Name: SED_PATT_H_Q0 Table 95. Bit Descriptions for SED_PATT_H_Q0 Bits Bit Name Description Reset Access [7:0] SED_PATTERN_FALL_Q0[15:8] SED Q0 falling edge high bits. 0x00 RW SED PATTERN I1 LOW BITS REGISTER Address: 0x65, Reset: 0x00, Name: SED_PATT_L_I1 Table 96. Bit Descriptions for SED_PATT_L_I1 Bits Bit Name Description Reset Access [7:0] SED_PATTERN_RISE_I1[7:0] SED I1 rising edge low bits. 0x00 RW SED PATTERN I1 HIGH BITS REGISTER Address: 0x66, Reset: 0x00, Name: SED_PATT_H_I1 Table 97. Bit Descriptions for SED_PATT_H_I1 Bits Bit Name Description Reset Access [2:0] SED_PATTERN_RISE_I1[15:8] SED I1 rising edge high bits. 0x00 RW SED PATTERN Q1 LOW BITS REGISTER Address: 0x67, Reset: 0x00, Name: SED_PATT_L_Q1 Table 98. Bit Descriptions for SED_PATT_L_Q1 Bits Bit Name Description Reset Access [7:0] SED_PATTERN_FALL_Q1[7:0] SED Q1 falling edge low bits. 0x00 RW Rev. A | Page 68 of 72 |
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