AD9142ABCPZRL datasheet(43/73 Pages) AD

43 / 73 page

AD9142A

Data Sheet

DAC INPUT CLOCK CONFIGURATIONS

The AD9142A DAC sample clock (DACCLK) can be sourced

directly or by clock multiplying. Clock multiplying employs the

on-chip PLL that accepts a reference clock operating at a

submultiple of the desired DACCLK rate. The PLL then

multiplies the reference clock up to the desired DACCLK

frequency, which can then be used to generate all of the internal

clocks required by the DAC. The clock multiplier provides a

high quality clock that meets the performance requirements of

most applications. Using the on-chip clock multiplier removes

the burden of generating and distributing the high speed DACCLK.

The second mode bypasses the clock multiplier circuitry and lets

DACCLK be sourced directly to the DAC core. This mode lets the

user source a very high quality clock directly to the DAC core.

DRIVING THE DACCLK AND REFCLK INPUTS

The DACCLKx and REFx/SYNCx differential inputs share

similar clock receiver input circuitry. Figure 53 shows a simplified

circuit diagram of the input. The on-chip clock receiver has a

differential input impedance of about 10 kΩ. It is self biased to a

common-mode voltage of about 1.25 V. The inputs can be

driven by differential PECL or LVDS drivers with ac coupling

between the clock source and the receiver.

Figure 53. Clock Receiver Input Simplified Equivalent Circuit

The minimum input drive level to the differential clock input is

100 mV p-p differential. The optimal performance is achieved

when the clock input signal is between 800 mV p-p differential

and 1.6 V p-p differential. Whether using the on-chip clock

multiplier or sourcing the DACCLK directly, the input clock

signal to the device must have low jitter and fast edge rates to

optimize the DAC noise performance.

DIRECT CLOCKING

Direct clocking with a low noise clock produces the lowest noise

spectral density at the DAC outputs. To select the differential

CLK inputs as the source for the DAC sampling clock, set the

PLL enable bit (Register 0x12[7]) to 0. This powers down the

internal PLL clock multiplier and selects the input from the

DACCLKP and DACCLKN pins as the source for the internal

DAC sampling clock. The REFCLKx input can remain floating.

The device also has clock duty cycle correction circuitry and

differential input level correction circuitry. Enabling these circuits

can provide improved performance in some cases. The control

bits for these functions are in Register 0x10 and Register 0x11.

CLOCK MULTIPLICATION

The on-chip PLL clock multiplier circuit generates the DAC

sample rate clock from a lower frequency reference clock. When

the PLL enable bit (Register 0x12[7]) is set to 1, the clock

multiplication circuit generates the DAC sampling clock from

the lower rate REFx/SYNCx input and the DACCLKx input is

left floating. The functional diagram of the clock multiplier is

shown in Figure 54.

The clock multiplier circuit operates such that the VCO outputs

a frequency, fVCO, equal to the REFx/SYNCx input signal

frequency multiplied by N1 × N0. N1 is the divide ratio of the

loop divider; N0 is the divide ratio of the VCO divider.

fVCO = fREFCLK × (N1 × N0)

The DAC sample clock frequency, fDACCLK, is equal to

fDACCLK = fREFCLK × N1

The output frequency of the VCO must be chosen to keep fVCO

in the optimal operating range of 1.03 GHz to 2.07 GHz. It is

important to select a frequency of the reference clock and values

of N1 and N0 so that the desired DACCLK frequency can be

synthesized and the VCO output frequency is in the correct range.

Figure 54. PLL Clock Multiplication Circuit

1.25V

5kΩ

100Ω

5kΩ

DACCLKP/

REFP/SYNCP

AD9142A

DACCLKN/

REFN/SYNCN

1~100nF

RECOMMENDED

EXTERNAL

CIRCUITRY

PHASE

FREQUENCY

DETECTION

CHARGE

PUMP

PLL CHARGE

PUMP CURRENT

REG 0x14[4:0]

DIVIDE BY

2, 4, 8, OR 16

LOOP DIVIDER

REG 0x15[1:0]

DIVIDE BY

1, 2, OR 4

VCO DIVIDER

REG 0x15[3:2]

ON-CHIP

LOOP FILTER

PLL LOOP BW

REG 0x14[7:5]

VCO

(1GHz~2.1GHz)

ADC

VCO CONTROL

VOLTAGE

REG 0x16[3:0]

REFP/SYNCP

(PIN 2)

REFN/SYNCN

(PIN 3)

DACCLKN

(PIN 62)

DACCLKP

(PIN 61)

DACCLK

PLL ENABLE

REG 0x12[7]

Rev. A | Page 42 of 72

AD9142ABCPZRL 数据表(PDF) 43 Page - Analog Devices

AD9142ABCPZRL 数据表(HTML) 43 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73

数据表下载