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AD9142ABCPZRL 数据表(PDF) 57 Page - Analog Devices

部件名 AD9142ABCPZRL
功能描述  Multiple chip synchronization
PDF  73 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD9142ABCPZRL 数据表(HTML) 57 Page - Analog Devices

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AD9142A
Data Sheet
DAC CLOCK RECEIVER CONTROL REGISTER
Address: 0x10, Reset: 0xFF, Name: DACCLK_RECEIVER_CTRL
Table 40. Bit Descriptions for DACCLK_RECEIVER_CTRL
Bits
Bit Name
Settings
Description
Reset
Access
7
DACCLK_DUTYCYCLE_CORRECTION
Enables duty cycle correction at the DACCLK input. For
best performance, the default and recommended status
is turned on.
1
RW
6
Reserved
Must write the default value for optimal performance
1
RW
5
DACCLK_CROSSPOINT_CTRL_ENABLE
Enables crosspoint control at the DACCLK input. For best
performance, the default and recommended status is
turned on.
1
RW
[4:0]
DACCLK_CROSSPOINT_LEVEL
A twos complement value. For best performance, it is
recommended to set DACCLK_CROSSPOINT_LEVEL to
the default value.
0x1F
RW
01111
Highest crosspoint.
11111
Lowest crosspoint.
REF CLOCK RECEIVER CONTROL REGISTER
Address: 0x11, Reset: 0x5F, Name: REFCLK_RECEIVER_CTRL
Table 41. Bit Descriptions for REFCLK_RECEIVER_CTRL
Bits
Bit Name
Settings
Description
Reset
Access
7
DUTYCYCLE_CORRECTION
Enables duty cycle correction at the REFx/SYNCx input.
For best performance, the default and recommended
status is turned off.
0
RW
6
Reserved
Must write the default value for optimal performance
1
RW
5
REFCLK_CROSSPOINT_CTRL_ENABLE
Enables crosspoint control at the REFx/SYNCx input. For
best performance, the default and recommended status
is turned off.
0
RW
[4:0]
REFCLK_CROSSPOINT_LEVEL
A twos complement value. For best performance, it is
recommended to set REFCLK_CROSSPOINT_LEVEL to
the default value.
0x1F
RW
01111
Highest crosspoint.
11111
Lowest crosspoint.
PLL CONTROL 0 REGISTER
Address: 0x12, Reset: 0x00, Name: PLL_CTRL0
Table 42. Bit Descriptions for PLL_CTRL0
Bits
Bit Name
Settings
Description
Reset
Access
7
PLL_ENABLE
Enables PLL clock multiplier.
0
RW
6
AUTO_MANUAL_SEL
PLL band selection mode.
0
RW
0
Automatic mode.
1
Manual mode.
[5:0]
PLL_MANUAL_BAND
PLL band setting in manual mode. 64 bands in total, covering a 1 GHz to
2.1 GHz VCO range.
0x00
RW
000000
Lowest band (1 GHz).
111111
Highest band (2.1 GHz).
Rev. A | Page 56 of 72



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