AD9142ABCPZRL datasheet(27/73 Pages) AD

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AD9142A

Data Sheet

DLL Configuration Example 1

In the following DLL configuration example, fDCI = 500 MHz,

DLL is enabled, and DLL phase offset = 0.

0x5E → 0xFE /* Turn off LSB delay cell*/

0x0D → 0x06 /* Select DLL configure

options */

0x0A → 0xC0 /* Enable DLL and duty cycle

correction. Set DLL phase offset to 0 */

Read 0x0E[7:4] /* Expect 1000b if the DLL

is locked */

DLL Configuration Example 2

In the following DLL configuration example, fDCI = 300 MHz,

DLL is enable, and DLL phase offset = 0.

0x5E → 0xFE /* Turn off LSB delay cell*/

0x0D → 0x86 /* Select DLL configure

options */

0x0A → 0xC0 /* Enable DLL and duty cycle

correction. Set DLL phase offset to 0 */

Read 0x0E[7:4] /* Expect 1000b if the DLL

is locked */

PARITY

The data interface can be continuously monitored by enabling

the parity bit feature in Register 0x6A, Bit 7 and configuring the

frame/parity bit as parity by setting Register 0x09 to 0x21. In

this case, the host sends a parity bit along with each data

sample. This bit is set according to the following formulas,

where n is the data sample that is being checked.

For even parity,

XOR[FRM(n), D0(n), D1(n), D2(n), ..., D15(n)] = 0

For odd parity,

XOR[FRM(n), D0(n), D1(n), D2(n), ..., D15(n)] = 1

The parity bit is calculated over 17 bits (including the

frame/parity bit).

If a parity error occurs, the parity error counter (Register 0x6B

or Register 0x6C) is incremented. Parity errors on the bits

sampled by the rising edge of DCI increments the rising edge

parity counter (Register 0x6B) and set the PARERRRIS bit

(Register 0x6A, Bit 0). Parity errors on the bits sampled by the

falling edge of DCI will increment the falling edge parity counter

(Register 0x6C) and set the PARERRFAL bit (Register 0x6A, Bit 1).

The parity counter continues to accumulate until it is cleared or

until it reaches a maximum value of 255. The count can be

cleared by writing a 1 to Register 0x6A, Bit 5.

To trigger an IRQ when a parity error occurs, write a 1 to

edge or falling edge parity error. The status of the IRQ can be

observed via Register 0x06, Bit 7 or by using the selected IRQx

pin. Clear the IRQ by writing a 1 to Register 0x06, Bit 7.

Use the parity bit to validate the interface timing. As described

previously, the host provides a parity bit with the data samples,

as well as configures the AD9142A to generate an IRQ. The user

can then sweep the sampling instance of the AD9142A input

registers to determine at what point a sampling error occurs.

The sampling instance can be varied in discrete increments by

offsetting the nominal DLL phase shift value of 90° via Register

0x0A[3:0].

SED OPERATION

The AD9142A provides on-chip sample error detection (SED)

circuitry that simplifies verification of the input data interface.

The SED compares the input data samples captured at the digital

input pins with a set of comparison values. The comparison values

are loaded into registers through the SPI port. Differences between

the captured values and the comparison values are detected.

Options are available for customizing SED test sequencing and

error handling.

The SED circuitry allows the application to test a short user

defined pattern to confirm that the high speed source

synchronous data bus is correctly implemented and meets the

timing requirement. Unlike the parity bit, the SED circuitry is

expected to be used during initial system calibration, before the

AD9142A is in use in the application. The SED circuitry

operates on a data set made up of user defined input words,

denoted as I0, Q0, I1, and Q1. The user defined pattern consists

of sequential data word samples (I0 is sampled on the rising

edge of DCI, Q0 is sampled on the following falling edge of

DCI, I1 is sampled on the following DCI rising edge, and Q1 is

sampled on the following DCI falling edge). The user loads this

data pattern in the byte format into Register 0x61 through

The depth of the user defined pattern is selectable via Bit 4 in

the SED_CTRL register (0x60), with the default, 0, meaning a

depth of two (using I0 and Q0), and a 1 meaning a depth of four

(using I0, Q0, I1, and Q1, and requiring the use of frame signal

input to define I0 to the SED state machine). To properly align

the input samples using a depth of four, I0 is indicated by

asserting the frame signal for a minimum of two complete input

samples as shown in Figure 37. The frame signal can be issued

once at the start of the data transmission, or it can be asserted

repeatedly at intervals coinciding with the S0 word.

Figure 37. Timing Diagram of Extended FRAME Signal Required to Align

Input Data for SED

The SED has three flag bits (Register 0x60, Bit 0, Bit 1, and Bit 2)

that indicate the results of the input sample comparisons. The

sample error detected bit (Register 0x60, Bit 0) is set when an

error is detected and remains set until cleared.

FRAME

DATA[15:0]

Rev. A | Page 26 of 72

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