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AD9142ABCPZRL 数据表(PDF) 64 Page - Analog Devices |
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AD9142ABCPZRL 数据表(HTML) 64 Page - Analog Devices |
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64 / 73 page  Data Sheet AD9142A INPUT POWER READBACK MSB REGISTER Address: 0x2D, Reset: 0x00, Name: INPUT_POWER_READBACK_MSB Table 68. Bit Descriptions for INPUT_POWER_READBACK_MSB Bits Bit Name Settings Description Reset Access [4:0] INPUT_POWER_READBACK_MSB These bits, along with Bits[7:0] in Register 0x2C, set the input signal average power readback. 0x00 R NCO CONTROL REGISTER Address: 0x30, Reset: 0x00, Name: NCO_CTRL Table 69. Bit Descriptions for NCO_CTRL Bits Bit Name Settings Description Reset Access 6 NCO_FRAME_UPDATE_ACK Frequency tuning word update request from frame. 0x0 R 5 SPI_NCO_PHASE_RST_ACK NCO phase SPI reset acknowledge. 0x0 R 4 SPI_NCO_PHASE_RST_REQ NCO phase SPI reset request. 0x0 RW 1 NCO_SPI_UPDATE_ACK Frequency tuning word update acknowledge. 0x0 R 0 NCO_SPI_UPDATE_REQ Frequency tuning word update request from SPI. 0x0 RW NCO FREQUENCY TUNING WORD 0 REGISTER Address: 0x31, Reset: 0x00, Name: NCO_FREQ_TUNING_WORD0 Table 70. Bit Descriptions for NCO_FREQ_TUNING_WORD0 Bits Bit Name Settings Description Reset Access [7:0] NCO_FTW0 Bits[7:0] together with the bits in Register 0x32, Register 0x33, and Register 0x34 form the 32-bit frequency tuning word that determines the frequency of the complex carrier generated by the on-chip NCO. The frequency is not updated when the FTW registers are written. The values are only updated when a serial port update or frame update is initialized in Register 0x30. It is in twos complement format. 0x00 RW NCO FREQUENCY TUNING WORD 1 REGISTER Address: 0x32, Reset: 0x00, Name: NCO_FREQ_TUNING_WORD1 Table 71. Bit Descriptions for NCO_FREQ_TUNING_WORD1 Bits Bit Name Settings Description Reset Access [7:0] NCO_FTW1 Bits[7:0] together with the bits in Register 0x31, Register 0x33, and Register 0x34 form the 32-bit frequency tuning word that determines the frequency of the complex carrier generated by the on-chip NCO. The frequency is not updated when the FTW registers are written. The values are only updated when a serial port update or frame update is initialized in Register 0x30. It is in twos complement format. 0x00 RW NCO FREQUENCY TUNING WORD 2 REGISTER Address: 0x33, Reset: 0x00, Name: NCO_FREQ_TUNING_WORD2 Table 72. Bit Descriptions for NCO_FREQ_TUNING_WORD2 Bits Bit Name Settings Description Reset Access [7:0] NCO_FTW2 Bits[7:0] together with the bits in Register 0x31, Register 0x32, and Register 0x34 form the 32-bit frequency tuning word that determines the frequency of the complex carrier generated by the on-chip NCO. The frequency is not updated when the FTW registers are written. The values are only updated when a serial port update or frame update is initialized in Register 0x30. It is in twos complement format. 0x00 RW Rev. A | Page 63 of 72 |
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