数据搜索系统，热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

预览 PDF HTML

EM357-RTR 数据表(PDF) 148 Page - Silicon Laboratories

部件名 EM357-RTR
功能描述  High-Performance, Integrated ZigBee/802.15.4 System-on-Chip
PDF  241 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  SILABS [Silicon Laboratories]
网页  http://www.silabs.com
标志 SILABS - Silicon Laboratories

EM357-RTR 数据表(HTML) 148 Page - Silicon Laboratories

Back Button EM357-RTR Datasheet HTML 144Page - Silicon Laboratories EM357-RTR Datasheet HTML 145Page - Silicon Laboratories EM357-RTR Datasheet HTML 146Page - Silicon Laboratories EM357-RTR Datasheet HTML 147Page - Silicon Laboratories EM357-RTR Datasheet HTML 148Page - Silicon Laboratories EM357-RTR Datasheet HTML 149Page - Silicon Laboratories EM357-RTR Datasheet HTML 150Page - Silicon Laboratories EM357-RTR Datasheet HTML 151Page - Silicon Laboratories EM357-RTR Datasheet HTML 152Page - Silicon Laboratories Next Button
Zoom Inzoom in Zoom Outzoom out
 148 / 241 page
background image
Rev 1.3
148
TIM1_SMCR: Address: 0x4000E008 Reset: 0x0
TIM2_SMCR: Address: 0x4000F008 Reset: 0x0
Register 9.3. TIMx_SMCR
TIM1_SMCR: Timer 1 Slave Mode Control Register
TIM2_SMCR: Timer 2 Slave Mode Control Register
Bit
31
30
29
28
27
26
25
24
Name
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
Name
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
Name
TIM_ETP
TIM_ECE
TIM_ETPS
TIM_ETF
Bit
7
6
5
4
3
2
1
0
Name
TIM_MSM
TIM_TS
0
TIM_SMS
Bitname
Bitfield
Access
Description
TIM_ETP
[15]
RW
External Trigger Polarity.
This bit selects whether ETR or the inverse of ETR is used for trigger opera-
tions.
0: ETR is non-inverted, active at a high level or rising edge.
1: ETR is inverted, active at a low level or falling edge.
TIM_ECE
[14]
RW
External Clock Enable.
This bit enables external clock mode 2.
0: External clock mode 2 disabled.
1: External clock mode 2 enabled. The counter is clocked by any active edge
on the ETRF signal.
Notes:
1.
Setting the TIM_ECE bit has the same effect as selecting external clock mode
1 with TRGI connected to ETRF (TIM_SMS=111 and TIM_TS=111).
2.
It is possible to use this mode simultaneously with the following slave modes:
reset mode, gated mode and trigger mode. TRGI must not be connected to
ETRF in this case (the TIM_TS bits must not be 111).
3.
If external clock mode 1 and external clock mode 2 are enabled at the same
time, the external clock input will be ETRF.
TIM_ETPS
[13:12]
RW
External Trigger Prescaler.
External trigger signal ETRP frequency must be at most 1/4 of CK frequency.
A prescaler can be enabled to reduce ETRP frequency. It is useful with fast
external clocks.
00: ETRP prescaler off.
01: Divide ETRP frequency by 2.
10: Divide ETRP frequency by 4.
11: Divide ETRP frequency by 8.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com