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EM357-RTR 数据表(PDF) 151 Page - Silicon Laboratories |
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EM357-RTR 数据表(HTML) 151 Page - Silicon Laboratories |
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151 / 241 page ![]() 151 Rev 1.3 TIM1_EGR: Address: 0x4000E014 Reset: 0x0 TIM2_EGR: Address: 0x4000F014 Reset: 0x0 Register 9.4. TIMx_EGR TIM1_EGR: Timer 1 Event Generation Register TIM2_EGR: Timer 2 Event Generation Register Bit 31 30 29 28 27 26 25 24 Name 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 Name 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 Name 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Name 0 TIM_TG 0 TIM_CC4G TIM_CC3G TIM_CC2G TIM_CC1G TIM_UG Bitname Bitfield Access Description TIM_TG [6] W Trigger Generation. 0: Does nothing. 1: Sets the TIM_TIF flag in the INT_TIMxFLAG register. TIM_CC4G [4] W Capture/Compare 4 Generation. 0: Does nothing. 1: If CC4 configured as output channel: The TIM_CC4IF flag is set. If CC4 configured as input channel: The TIM_CC4IF flag is set. The INT_TIMMISSCC4IF flag is set if the TIM_CC4IF flag was already high. The current value of the counter is captured in TMRx_CCR4 register. TIM_CC3G [3] W Capture/Compare 3 Generation. 0: Does nothing. 1: If CC3 configured as output channel: The TIM_CC3IF flag is set. If CC3 configured as input channel: The TIM_CC3IF flag is set. The INT_TIMMISSCC3IF flag is set if the TIM_CC3IF flag was already high. The current value of the counter is captured in TMRx_CCR3 register. |
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