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ADAU1772BCPZ-R7 数据表(PDF) 106 Page - Analog Devices

部件名 ADAU1772BCPZ-R7
功能描述  Four ADC, Two DAC Low Power Codec
PDF  117 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADAU1772BCPZ-R7 数据表(HTML) 106 Page - Analog Devices

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Data Sheet
ADAU1772
Rev. C | Page 105 of 116
DECIMATOR POWER CONTROL REGISTER
Address: 0x0044, Reset: 0x00, Name: DECIM_PWR_MODES
These bits enable clocks to the digital filters and ASRC decimator filters of the ADCs. These bits must be enabled for all channels that will be used
in the design. To use the ADCs, these SINC_x_EN bits must be enabled along with the appropriate ADC_x_EN bits in the ADC_CONTROL2
and ADC_CONTROL3 registers. If the digital microphone inputs are used, the SINC_x_EN bits can be set without setting ADC_x_EN.
Table 95. Bit Descriptions for DECIM_PWR_MODES
Bits
Bit Name
Settings
Description
Reset
Access
7
DEC_3_EN
Control power to the ASRC3 decimator.
0x0
RW
0
Powered down
1
Powered up
6
DEC_2_EN
Control power to the ASRC2 decimator.
0x0
RW
0
Powered down
1
Powered up
5
DEC_1_EN
Control power to the ASRC1 decimator.
0x0
RW
0
Powered down
1
Powered up
4
DEC_0_EN
Control power to the ASRC0 decimator.
0x0
RW
0
Powered down
1
Powered up
3
SINC_3_EN
ADC3 filter power control.
0x0
RW
0
Powered down
1
Powered up
2
SINC_2_EN
ADC2 filter power control.
0x0
RW
0
Powered down
1
Powered up
1
SINC_1_EN
ADC1 filter power control.
0x0
RW
0
Powered down
1
Powered up
0
SINC_0_EN
ADC0 filter power control.
0x0
RW
0
Powered down
1
Powered up



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