Z8F021ASH020SC datasheet(104/276 Pages) ZILOG

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PS022815-0206

Watch-Dog Timer

Z8 Encore! XP® 4K Series

Product Specification

WDT Interrupt in STOP Mode

If configured to generate an interrupt when a time-out occurs and the Z8 Encore! XP® 4K

Series devices are in STOP mode, the Watch-Dog Timer automatically initiates a STOP

Mode Recovery and generates an interrupt request. Both the WDT status bit and the STOP

bit in the Reset Status (RSTSTAT) register are set to 1 following a WDT time-out in STOP

mode. Refer to the chapter Reset, STOP Mode Recovery and Low Voltage Detection on

page 20 for more information about STOP Mode Recovery.

If interrupts are enabled, following completion of the STOP Mode Recovery the eZ8 CPU

responds to the interrupt request by fetching the Watch-Dog Timer interrupt vector and

executing code from the vector address.

WDT Reset in NORMAL Operation

If configured to generate a Reset when a time-out occurs, the Watch-Dog Timer forces the

device into the System Reset state. The WDT status bit in the Reset Status (RSTSTAT)

Detection on page 20 for more information about system reset.

WDT Reset in STOP Mode

If configured to generate a Reset when a time-out occurs and the device is in STOP mode,

the Watch-Dog Timer initiates a STOP Mode Recovery. Both the WDT status bit and the

STOP

bit in the Reset Status (RSTSTAT) register are set to 1 following WDT time-out in

STOP mode. Refer to the chapter Reset, STOP Mode Recovery and Low Voltage Detec-

tion on page 20 for more information.

Watch-Dog Timer Reload Unlock Sequence

Writing the unlock sequence to the Watch-Dog Timer (WDTCTL) Control register address

unlocks the three Watch-Dog Timer Reload Byte registers (WDTU, WDTH, and WDTL)

to allow changes to the time-out period. These write operations to the WDTCTL register

address produce no effect on the bits in the WDTCTL register. The locking mechanism

prevents spurious writes to the Reload registers. The following sequence is required to

unlock the Watch-Dog Timer Reload Byte registers (WDTU, WDTH, and WDTL) for

write access.

1. Write 55H to the Watch-Dog Timer Control register (WDTCTL).

2. Write AAH to the Watch-Dog Timer Control register (WDTCTL).

3. Write the Watch-Dog Timer Reload Upper Byte register (WDTU).

4. Write the Watch-Dog Timer Reload High Byte register (WDTH).

5. Write the Watch-Dog Timer Reload Low Byte register (WDTL).

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