Z8F021ASH020SC datasheet(106/276 Pages) ZILOG

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PS022815-0206

Watch-Dog Timer

Z8 Encore! XP® 4K Series

Product Specification

WDTUNLK—Watch-Dog Timer Unlock

The user software must write the correct unlocking sequence to this register before it is

allowed to modify the contents of the watch-dog timer reload registers.

Watch-Dog Timer Reload Upper, High and Low Byte Registers

The Watch-Dog Timer Reload Upper, High and Low Byte (WDTU, WDTH, WDTL) reg-

isters (Tables 59 through 61) form the 24-bit reload value that is loaded into the Watch-

Dog Timer when a WDT instruction executes. The 24-bit reload value is {WDTU[7:0],

WDTH[7:0], WDTL[7:0]}. Writing to these registers sets the appropriate Reload Value.

Reading from these registers returns the current Watch-Dog Timer count value.

The 24-bit WDT Reload Value must not be set to a value less than 000004H.

WDTU—WDT Reload Upper Byte

Most significant byte (MSB), Bits[23:16], of the 24-bit WDT reload value.

WDTH—WDT Reload High Byte

Middle byte, Bits[15:8], of the 24-bit WDT reload value.

Table 59. Watch-Dog Timer Reload Upper Byte Register (WDTU)

BITS

FIELD

WDTU

RESET

FFH

R/W

R/W*

ADDR

FF1H

R/W* - Read returns the current WDT count value. Write sets the appropriate Reload Value.

Table 60. Watch-Dog Timer Reload High Byte Register (WDTH)

BITS

FIELD

WDTH

RESET

FFH

R/W

R/W*

ADDR

FF2H

R/W* - Read returns the current WDT count value. Write sets the appropriate Reload Value.

Caution:

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