Z8F021ASH020SC datasheet(105/276 Pages) ZILOG

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PS022815-0206

Watch-Dog Timer

Z8 Encore! XP® 4K Series

Product Specification

All three Watch-Dog Timer Reload registers must be written in the order just listed. There

must be no other register writes between each of these operations. If a register write

occurs, the lock state machine resets and no further writes can occur unless the sequence is

restarted. The value in the Watch-Dog Timer Reload registers is loaded into the counter

when the Watch-Dog Timer is first enabled and every time a WDT instruction is executed.

Watch-Dog Timer Calibration

Due to its extremely low operating current, the Watch-Dog Timer oscillator is somewhat

inaccurate. This variation can be corrected using the calibration data stored in the Flash

Information Page (see Tables 98 and 99 on page 158). Loading these values into the

Watch-Dog Timer Reload Registers will result in a one-second timeout at room tempera-

ture and 3.3V supply voltage.

Timeouts other than one second may be obtained by scaling the calibration values up or

down as required. Note that the Watch-Dog Timer accuracy will still degrade as tempera-

ture and supply voltage vary. See Table 136, Watch-Dog Timer Electrical Characteristics

and Timing on page 220 for details.

Watch-Dog Timer Control Register Definitions

Watch-Dog Timer Control Register

The Watch-Dog Timer Control (WDTCTL) register is a write-only control register. Writ-

ing the 55H, AAH unlock sequence to the WDTCTL register address unlocks the three

Watch-Dog Timer Reload Byte registers (WDTU, WDTH, and WDTL) to allow changes

to the time-out period. These write operations to the WDTCTL register address produce

no effect on the bits in the WDTCTL register. The locking mechanism prevents spurious

writes to the Reload registers.

This register address is shared with the read-only Reset Status Register.

Table 58. Watch-Dog Timer Control Register (WDTCTL)

BITS

FIELD

WDTUNLK

RESET

XXX

R/W

WWW

ADDR

FF0H

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