Z8F021ASH020SC datasheet(139/276 Pages) ZILOG

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PS022815-0206

Analog-to-Digital Converter

Z8 Encore! XP® 4K Series

Product Specification

120

where GAINCAL is the gain calibration value, OFFCAL is the offset calibration value

and ADCuncomp is the uncompensated value read from the ADC. All values are in

two’s complement format.

The offset compensation is performed first, followed by the gain compensation. One

bit of resolution is lost because of rounding on both the offset and gain computations.

As a result the ADC registers read back 13 bits: 1 sign bit, two calibration bits lost to

rounding and 10 data bits.

Also note that in the second term, the multiplication should be performed before the

division by 216. Otherwise, the the second term will incorrectly evaluate to zero.

Although the ADC can be used without the gain and offset compensation, it does exhibit

non-unity gain. Designing the ADC with sub-unity gain reduces noise across the ADC

range but requires the ADC results to be scaled by a factor of 8/7.

ADC Compensation Details

High efficiency assembly code that performs this compensation is available for download

on www.zilog.com. The following is a bit-specific description of the ADC compensation

process used by this code.

The following data bit definitions are used:

0-9, a-f = bit indices in hexadecimal

s = sign bit

v = overflow bit

- = unused

Input Data:

MSB

LSB

s b a 9 8 7 6 5

4 3 2 1 0 - - v (ADC)

ADC Output Word; if v = 1,

the data is invalid

s 6 5 4 3 2 1 0

Offset Correction Byte

s s s s s 7 6 5

4 3 2 1 0 0 0 0 (Offset)

Offset Byte shifted to align

with ADC data

s e d c b a 9 8

7 6 5 4 3 2 1 0 (Gain)

Gain Correction Word

Note:

Caution:

Z8F021ASH020SC 数据表(PDF) 139 Page - Zilog, Inc.

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