Z8F021ASH020SC datasheet(188/276 Pages) ZILOG

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PS022815-0206

On-Chip Debugger

Z8 Encore! XP® 4K Series

Product Specification

169

Figure 25.Interfacing the On-Chip Debugger’s DBG Pin with an RS-232 Interface (2)

DEBUG Mode

The operating characteristics of the devices in DEBUG mode are:

• The eZ8 CPU fetch unit stops, idling the eZ8 CPU, unless directed by the OCD to execute

specific instructions

• The system clock operates unless in STOP mode

• All enabled on-chip peripherals operate unless in STOP mode

• Automatically exits HALT mode

• Constantly refreshes the Watch-Dog Timer, if enabled

Entering DEBUG Mode

• The device enters DEBUG mode after the eZ8 CPU executes a BRK (Breakpoint) instruc-

tion.

• If the DBG pin is held Low during the most recent clock cycle of system reset, the part

enters DEBUG mode upon exiting system reset. (20-/28-pin products only.)

• If the PA2/RESET pin is held Low while a 32-bit key sequence is issued to the PA0/DBG

pin, the DBG feature is unlocked. After releasing PA2/RESET, it will be pulled high. At

this point, the PA0/DBG pin may be used to autobaud and cause the device to enter DE-

BUG mude. See OCD Unlock Sequence (8-Pin Devices Only) on page 171.

Exiting DEBUG Mode

The device exits DEBUG mode following any of these operations:

• Clearing the DBGMODE bit in the OCD Control Register to 0.

RS-232 TX

RS-232 RX

RS-232

Transceiver

VDD

DBG Pin

10KOhm

Open-Drain

Buffer

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