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Z8F021ASH020SC 数据表(PDF) 190 Page - Zilog, Inc.

部件名 Z8F021ASH020SC
功能描述  Z8 Encore XP-R 4K Series High-Performance 8-Bit Microcontrollers
PDF  276 Pages
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制造商  ZILOG [Zilog, Inc.]
网页  http://www.zilog.com
标志 ZILOG - Zilog, Inc.

Z8F021ASH020SC 数据表(HTML) 190 Page - Zilog, Inc.

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PS022815-0206
On-Chip Debugger
Z8 Encore! XP® 4K Series
Product Specification
171
If the OCD receives a Serial Break (nine or more continuous bits Low) the Auto-Baud
Detector/Generator resets. Reconfigure the Auto-Baud Detector/Generator by sending
80H
.
OCD Serial Errors
The On-Chip Debugger can detect any of the following error conditions on the DBG pin:
• Serial Break (a minimum of nine continuous bits Low)
• Framing Error (received Stop bit is Low)
• Transmit Collision (OCD and host simultaneous transmission detected by the OCD)
When the OCD detects one of these errors, it aborts any command currently in progress,
transmits a four character long Serial Break back to the host, and resets the Auto-Baud
Detector/Generator. A Framing Error or Transmit Collision may be caused by the host
sending a Serial Break to the OCD. Because of the open-drain nature of the interface,
returning a Serial Break break back to the host only extends the length of the Serial Break
if the host releases the Serial Break early.
The host transmits a Serial Break on the DBG pin when first connecting to the Z8 Encore!
XP® 4K Series devices or when recovering from an error. A Serial Break from the host
resets the Auto-Baud Generator/Detector but does not reset the OCD Control register. A
Serial Break leaves the device in DEBUG mode if that is the current mode. The OCD is
held in Reset until the end of the Serial Break when the DBG pin returns High. Because of
the open-drain nature of the DBG pin, the host can send a Serial Break to the OCD even if
the OCD is transmitting a character.
OCD Unlock Sequence (8-Pin Devices Only)
Because of pin-sharing on the 8-pin device, an unlock sequence must be performed to
access the DBG pin. If this squence is not completed during a system reset, then the PA0/
DBG pin functions only as a GPIO pin.
The following sequence unlocks the DBG pin:
1. Hold PA2/RESET Low.
1.0
125.0
115,200
1.95
0.032768 (32KHz)
4.096
2400
0.064
Table 108. OCD Baud-Rate Limits
System Clock Frequency
(MHz)
Recommended
Maximum Baud
Rate (Kbps)
Recommended
Standard PC Baud
Rate (bps)
Minimum Baud
Rate (Kbps)



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